Hi everyone!
I usually use the instruction CPS to switch working states form PL1 to PL0, or switch between PL1s. How many clock cycles does it take?
Based on Cortex-R5, will it take a long time？
Thanks.
I think you want this section of the Cortex-R5's Technical Reference Manual (TRM):
https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/Processor-state-updating-instructions?lang=enBut note there's more to it than just the cycles needed by the core. There's the dual issue rules (https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/Dual-issue?lang=en), whether you hit/miss in the cache, etc...
Thank you very much! Very helpful.