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I'm a hw designer and using Layerscape LS1027A dual Cortex A72 core SoC in a new design. The question is how this specific processor determines the execution state (AArch32 vs. AArch64) during boot time. According to the ARM specification during powerup and on reset, the processor enters EL3, the highest Exception level. The Execution state for this Exception level is controlled by the configuration input signal, AA64nAA32. However, I have not found any further information on this AA64nAA32 signal. Is this a kind of hw signal I have to take care? How can I set the required state of this signal? I have not used ARM before, any inputs are much appreciated!
Hi DigiTom,
The Cortex-A72 TRM documents those input signals:
Individual core register width state. The register width states are:
This signal is only sampled during powerup reset of the processor.
Best regards,
Vincent.