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Hi,
I am currently working on enabling SMMU-v3 in hypervisor, I notice in SMMU-v3, there are several memory attribute configuration options.
1. SMMU_CR1
a. TABLE_SH for Table access Shareability
b. TABLE_OC for Table access Outer Cacheability
c. TABLE_IC for Table access Inner Cancheability.
same configurations for queue access( QUEUE_SH, QUEUE_OC, QUEUE_IC)
---------------------------
/* CR1 (table and queue memory attributes) */
reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) |
(CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) |
(CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) |
(CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) |
(CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) |
(CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT);
writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
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always configure the register with the dedicated value without thinking about SMMU_IDR0 COHACC, bit [4]( Coherent access supported to translations, structures and queues.), if there is one SMMU with COHACC as 0, do not support Coherent access, it can only use non-cacheable memory, but the cr1 always configured with cacheablity, does the SMMU works properly?
2. STE
a. [169:168] S2IR0 for Inner region Cacheability for stage 2 translation table access.
b. [171:170] S2OR0 for Outer region Cacheability for stage 2 translation table access.
c. [173:172] S2SH0 for Shareability for stage 2 translation table access
thanks