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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3588 Questions
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  • Not Answered

    Options based on Cortex-M or Cortex-R for use with Pico and Nano Satelites. 0

    • Cortex-R
    • Cortex-M
    5151 views
    3 replies
    Latest over 10 years ago
    by Carlos Delfino
  • Answered

    Addressing memory question for Cortex-M3 0

    • Cortex-M3
    • Cortex-M
    10775 views
    2 replies
    Latest over 10 years ago
    by Merle Wagner
  • Answered

    Real Value of PC Register. 0

    • 32-bit
    • Cortex-M3
    • Thumb
    • Cortex-M
    9588 views
    4 replies
    Latest over 10 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    ARM TrustZone's Secure/Normal world vs x86's Ring0/3 or OS's kernel/user mode? +1

    • TrustZone
    • Linux
    10476 views
    2 replies
    Latest over 10 years ago
    by daith
  • Answered

    What does "low interrupt latency" means 0

    • Cortex-R
    • AXI
    • Cortex-R4
    14527 views
    11 replies
    Latest over 10 years ago
    by daith
  • Answered

    Difference between revisions 0

    • Cortex-A15
    • Cortex-A
    5235 views
    2 replies
    Latest over 10 years ago
    by Mohamed
  • Answered

    vfp problem +1

    • Cortex-M
    • Cortex-M4
    4153 views
    3 replies
    Latest over 10 years ago
    by daith
  • Answered

    How to test " Lock-Step " is working on Cortex-R5 ? 0

    • Cortex-R
    • Cortex-R5
    4728 views
    1 reply
    Latest over 10 years ago
    by Jon Taylor Arm Employee Badge
  • Answered

    ARMv7 performance monitor:how to get L2 cache refill? 0

    • Cortex-A9
    • Cache
    • Cortex-A
    6582 views
    2 replies
    Latest over 10 years ago
    by hello_arm
  • Answered

    Lock-Step mode execution on Cortex-R5 0

    • Cortex-R
    • Cortex-R5
    30379 views
    5 replies
    Latest over 10 years ago
    by Ravinder
  • Answered

    I am very new to ARM, still understanding the terminologies. What is the difference b/w the Cortex family and the x-gene? 0

    • Cortex-A53
    • Cortex-R
    • Cortex-M3
    • Armv8-A
    • Cortex-A
    • Cortex-M
    10499 views
    7 replies
    Latest over 10 years ago
    by daith
  • Answered

    Why Cortex-R series is real time oriented ? 0

    • Cortex-R
    • Memory Management Unit (MMU)
    • Cortex-A
    • Linux
    20644 views
    5 replies
    Latest over 10 years ago
    by Ravinder
  • Answered

    Why A9 is multicore by A8 doesn't +1

    • Cortex-A9
    • Cache coherency
    • Cortex-A
    • Cortex-A8
    6050 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    ARMv6 performance monitor: Can I record the instruction which caused the data cache miss 0

    • Cache
    • Arm11
    7231 views
    6 replies
    Latest over 10 years ago
    by Zhan Chen
  • Answered

    CPI for ARM V-7 0

    • Armv7
    7595 views
    4 replies
    Latest over 10 years ago
    by techguyz
  • Answered

    Minimal Frequency of Operation 0

    • Armv7
    • Cortex-A
    • Cortex-A8
    10088 views
    6 replies
    Latest over 10 years ago
    by Matthijs van Duin
  • Answered

    Problems with interrupting LDM/STM Cortex M4? +1

    • Armv7-M
    • Cortex-M
    • Cortex-M4
    24608 views
    18 replies
    Latest over 10 years ago
    by Graham Cunningham Arm Employee Badge
  • Answered

    Bare Metal Input/Output - Documentation? 0

    • AMBA
    • ACE
    • AXI
    9116 views
    6 replies
    Latest over 10 years ago
    by Matthijs van Duin
  • Answered

    Is there a list of direct addressing in assembler ? 0

    • GPIO
    • CMSIS
    5901 views
    5 replies
    Latest over 10 years ago
    by Jerome Decamps - 杜尚杰
  • Answered

    Cortex-M MPU limitations +1

    • Cortex-M7
    • Cortex-M
    8290 views
    3 replies
    Latest over 10 years ago
    by Joseph Yiu Arm Employee Badge
<>
Topics being discussed in this forum
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