I believe that many of us are interested in the ARM Cortex-M7.
Recently, jyiu posted a status update, where I asked a couple of questions about the architecture.
A few questions on the subject was also asked in the Interview and Question Time with Joseph Yiu discussion.
As I think the information posted is important and relevant, I'm posting a shortened version here, so it's easier to find.
Links:
Cortex-M7 Processor - ARM
ARM Cortex-M7 Processor Technical Reference Manual
ARMv7-M Reference Manual (Issue E.b)
AnandTech | Cortex-M7 Launches: Embedded, IoT and Wearables
ARM Supercharges MCU Market with High Performance Cortex-M7 Processor
ARM gives Internet of Things a piece of its mind – the Cortex-M7
STM32F7 von STMicroelectronics: ARMs Cortex-M7 (this article is in german)
Freescale Plans Extreme Performance for Kinetis MCUs with ARM® Cortex®-M7 Core
ARM Cortex-M - Wikipedia
NEW App Note: Migrating Application Code from ARM Cortex-M4 to Cortex-M7 Processors
Meet the new ARM Cortex-M7 processor: supercharging embedded devices
Atmel launches new series ARM Cortex-M7 based MCUs
As you see, STMicroelectronics will be releasing their first Cortex-M7 soon; Microchip and Freescale are also close.
Move the mouse over green-coloured abbreviations, in order to see what they mean.
Q: The Cortex-M7 now has a Branch Predictor and a BTAC. Does this mean that branches use 1 clock cycle only (or perhaps even below) ?
A: Yes, if correctly predicted the branch instruction is only 1 cycle.
Q: Does the 6-stage pipeline mean that loads can be archieved in a single cycle as well ?
A: Load from TCM is pipelined with other operations, so essentially single cycle or even less due to dual issue.
Q: The Cortex-M7 should be able to run at speeds up to 400Mhz, is that correct ?
A: In term of clock frequency, it is dependent on the semiconductor process nodes.
400MHz is the estimation for 40nm low power (LP) process. If using 28nm (e.g. 28hpm) or 14nm, the clock frequency can go much higher.
Q: From what I've heard, Interrupt latency is sometimes 12, sometimes 11 clock cycles; depending on the situation ?
A: The interrupt latency is a complex topic because it depends on how the memory system design looks.
The complete picture is fairly complex and I think we will need to create a separate document for that.
Q: Is it possible to move data directly between general purpose registers and floating point (single/double precision) registers without storing the data in memory first ?
A: The VMOV instruction (which exists on the Cortex-M4 already) allows data value to be transferred between general registers and floating point registers.
According to the Wikipedia, the Cortex-M7 supports the same instruction set as Cortex-M4F. I do not know if there are any additions to the instruction set, but I would expect that in order to use double-precision floating points and because of the enhanced DSP Extensions and BPU, there might be a few extra (I'm only guessing here).
Personally, I look very much forward to using the Branch Predictor, BTAC, the 6-stage superscalar pipeline, the dual integer pipe ALU, the higher speed, the double-precision floating point and the FPP.
If you have some technical information, I'd like to encourage you to post it here.