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hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

Firstly, i very wonder AWID, WID and BID when write transaction is started.

We assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are. 

The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ? also, is the RID value? similarly, does the RID value have the same AWID value ( 0x0001) ?




Secondly, we assume that burst transaction is started.

Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?

I totally want to know about the situation.

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  • Dear. Yasuhiko Koumoto

    Thank you for your solutions whenever i ask the AMBA 3.0 AXI.

    i will enter the master's degree. so i don't have a lot of information about AXI.

    Whenever i encounter the problem, i visit ARM community. And i post my problem on the community.

    you are very kind, polite and good! your response is very helpful to me!


    本当にありがとうございます。熱心に勉強します。

     

    from In-Gyu.Lee

Reply
  • Dear. Yasuhiko Koumoto

    Thank you for your solutions whenever i ask the AMBA 3.0 AXI.

    i will enter the master's degree. so i don't have a lot of information about AXI.

    Whenever i encounter the problem, i visit ARM community. And i post my problem on the community.

    you are very kind, polite and good! your response is very helpful to me!


    本当にありがとうございます。熱心に勉強します。

     

    from In-Gyu.Lee

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