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hi. i wonder AMBA 3.0 AXI handshake

In-Gyu.Lee

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

   

firstly, i very wonder the handshake when write transaction is started. if AWVALID signal and AWREADY signal still are not asserted when WVALID signal and WREADY signal are asserted, could BVALID signal assert then?

    

   

secondly, in timing picture of write burst transaction, WVALID signal and WREADY signal are asserted when first data transfers. if write address transaction is not started, does the first data is maintain until write address transaction is finished ?

   

finally, I wonder WLAST signal and RLAST signal. a master specify burst size and burst length to AWLEN, AWSIZE, ARLEN and ARSIZE. but master or slave assert WLAST or RLAST when final data are transferred. but we can know end of date burst by calculating burst size. I don’t know why AXI needs LAST signals.

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    Hello,

    firstly, i very wonder the handshake when write transaction is started. if AWVALID signal and AWREADY signal still are not asserted when WVALID signal and WREADY signal are asserted, could BVALID signal assert then?

    If the WLAST & WVALID & WREADY are already asserted, a slave can assert BVALID.

    A master can wait for BVALID after asserting WLAST & WVALID.

    secondly, in timing picture of write burst transaction, WVALID signal and WREADY signal are asserted when first data transfers. if write address transaction is not started, does the first data is maintain until write address transaction is finished ?

     
    No. the first data is accepted when the WREADY is asserted.

    finally, I wonder WLAST signal and RLAST signal. a master specify burst size and burst length to AWLEN, AWSIZE, ARLEN and ARSIZE. but master or slave assert WLAST or RLAST when final data are transferred. but we can know end of date burst by calculating burst size. I don’t know why AXI needs LAST signals.

    It is because of easing to design a master or slave.

    A slave is not required to use the WLAST signal. Since the length of a write burst is defined, a slave can calculate the last write data transfer from the burst length AWLEN signals.
    A master is not required to use the RLAST signal. Since the length of a read burst is defined, a master can calculate the last read data transfer from the burst length ARLEN signals.

    Best regards,

    Yasuhiko Koumoto.