• State Accepted Answer
  • Locked Locked
  • Replies 2 replies
  • Subscribers 349 subscribers
  • Views 5573 views
  • Users 0 members are here
Options
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

D-side prefetch Cortex-A8

Andreas Hauser

Hi at all!

At the moment I implement the initial routines and cache-handling for Cortex-A8. All the implementation is according the Boot-Code example in Cortex-A8 Programmers Guide on page 13-4.

Now I'm a little bit confused about the handling for enabling D-side prefetch.

The code read the Auxiliary-Control-Register and set bit number 2.

MRC p15, 0, r1, c1, c0, 1 @ Read Auxiliary Control Register

ORR r1, r1, #(0x1 <<2) @ Enable D-side prefetch

MCR p15, 0, r1, c1, c0, 1 ;@ Write Auxiliary Control Register

DSB

ISB


According to the TRM on page 3-48 (3-51) bit number 2 is reserved.

Also in some other implementations of cache handling I can find these confusing handling.

Can anyone help?

Thanks,

Andreas

0