hi. i wonder AMBA 3.0 AXI handshake

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

firstly, i very wonder the handshake when write transaction is started. if AWVALID signal and AWREADY signal still are not asserted when WVALID signal and WREADY signal are asserted, could BVALID signal assert then?

secondly, in timing picture of write burst transaction, WVALID signal and WREADY signal are asserted when first data transfers. if write address transaction is not started, does the first data is maintain until write address transaction is finished ?

finally, I wonder WLAST signal and RLAST signal. a master specify burst size and burst length to AWLEN, AWSIZE, ARLEN and ARSIZE. but master or slave assert WLAST or RLAST when final data are transferred. but we can know end of date burst by calculating burst size. I don’t know why AXI needs LAST signals.