Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.
Firstly, i very wonder AWID, WID and BID when write transaction is started.
We assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are.
The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ? also, is the RID value? similarly, does the RID value have the same AWID value ( 0x0001) ?
Secondly, we assume that burst transaction is started.
Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?
I totally want to know about the situation.
Hello anytime2736,
firstly, i very wonder AWID, WID and BID when write transaction is started. we assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are. The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ?
firstly, i very wonder AWID, WID and BID when write transaction is started.
we assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are.
The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ?
First of all, AXI has the multi-layer bus scheme and almost all timing charts are the views by a slave.
The slave will receive several couples of transaction from several masters.
The IDs are needed to distinguish every transaction.
Therefore the AWID, WID and BID should be the same.
For example the following case would be considered.
also, is the RID value?
What is the purpose of the question?
ARID and RID should be the same to distinguish the data corresponding to its address.
AWID and ARID might not be the same.
However the read and the write are independent.
similarly, does the RID value have the same AWID value ( 0x0001) ?
The read channel and the write channel are independent and (ARID, RID) may not be the same as (AWID, WID and BID).
secondly, we assume that burst transaction is started. Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?
secondly, we assume that burst transaction is started.
WID and RID have to be generated whenever one of burst data is transferred because the issued WDATAs or RDATA responces woulld out-of-order.
I hope my answers will match your intention.
Best regards,
Yasuhiko Koumoto.
Dear. Yasuhiko Koumoto
Hello
your opinion is very helpful to me! i wrote RID before a question. it is a typing error. i'm very sorry.
i have one more question. i wonder about interleaving and out-of order.
AXI supports out-of order and interleaving. read transaction and write transaction enable out-of order.
does interleaving be enable only write transaction?
also, the masters have slave interface including write interleaving depth. if a salve interface attaching a master(M0) has write interleaving depth of two, can the master(M0) process write data interleaving about write data having different ID filed?
From. In-Gyu. Lee
Hello, In-Gyu, Lee.
AXI supports out-of order and interleaving. read transaction and write transaction enable out-of order. does interleaving be enable only write transaction?
The interleaving is a concept only for write. It is not an interleaving but a write interleaving.
The write interleaving means a master will issue write data separately for one transaction.
The out-of-order means a relationship between address and data.
On an AXI bus, IDs indicates the correspondence between addresses and data.
Therefore, the order of addresses and data is independent.
The depth of the write interleaving is a concept of a slave.
It means how many transactions (i.e. the number of addresses) a slave can accept.
I think you probably say the number of out-standings of a master by the words of the write interleaving depth.
Of course the two write transactions which will both be the write interleaved should use different ID for each write transaction.
If the same IDs were used, a slave could not distinguish that the write transaction had been interleaved.
i add one question.
you said that Write interleaving depth is how many transactions a slave can accept.
as you can see the picture, Slave interface 0 and Slave inter face 1 have Write interleaving depth of 1.
what does Write interleaving depth of 1 mean?
i understood Master interface1 having Write interleave capability of 2 and Slave1 having Write interleaving depth of 2.
but Write interleaving depth included in Slave interface0 didn't understand.
please talk to me about correct information.
Dear Yasuhiko Koumoto
Hello!
you told me that the interleaving is a concept only for write. but i saw AMBA 3.0 AXI Spec. It has been described as shown below.
i understood that read transactions enable interleaving. because this sentence has been described "it is acceptable to interleave the read data of transactions with different ARID fields."
what does "interleave" mean?
according to your opinion, this situation is not permitted below the picture.
correct? ( this picture was drawn by me. i assume that read transaction is and all transactions have different IDs )
from In-Gyu.Lee
thank you very much whenever you give the solution to me.
Hello In-Gyu.Lee.
The meaning of "Write interleaving depth of 1" is that each slave can accept only one interleaved write.
Otherwise, "Write interleaving capability of 2" is a concept for a master, which might issue 2 out-standing interleaved writes,
As for the slave interfaces of the INTERCONNECT permit 1 + 1 interleave depth and the master interface to the Slave 1 of the INTERCONNECT should be permit at least 2 interleave depth.
The write interleaving depth information would be needed to design a slave which will be connected to a master of the INTERCONNECT.
the scenario is permitted because if is just only the out-of-order response case.
The write interleaving indicated that 1 write transaction data will be divided into several units for a master.
The ordering of RDATA or BRESP form a slave might be out-of-order for each master.
i understood that "it is just only the out-of-order response".
but i saw data interleaving in the first picture. also, in the second picture, A0 and A1 data are interleaved between B0 and B1.
is it possible??????
i think that it's impossible. because, in first picture, D31 and D32 data have to process in order without interleaving D11 ~D14 data. correct?
also i ask the two scenario. ( i assume that read transaction and all transaction have different IDs)
as you can see the first picture, i wrote "Data interleaving" . is it write data interleaving??
as you can see the second picture, i drawn the write transaction. is the scenario correct about Out-of-order and Write data interleaving in this picture?
Hello,
but i saw data interleaving in the first picture. also, in the second picture, A0 and A1 data are interleaved between B0 and B1. is it possible??????
First of all, the data interleaving and the write interleaving are different concept.
So, it is possible.
The master should gather read response data corresponding to each address by using RID.
I will be possible.
How come are you so sure?
The D31 and D32 will be processed in order even with data interleaving of D11 to D14 because data response with RID of 0x001 are returned in order.
Why do you think " D31 and D32 data have to process in order without interleaving"?
I'm sorry but I cannot understand what the two scenario are.
The picture shows the tow write interleaving but what you indicate is a just the first data.
It might be said correct.
The picture also shows the two write interleaving.
Of course, it shows the out-of-order write response.
Please tell me what parts of my comments are incorrect.
I think I had shown no incorrect information.
Thank you for your solutions whenever i ask the AMBA 3.0 AXI.
i will enter the master's degree. so i don't have a lot of information about AXI.
Whenever i encounter the problem, i visit ARM community. And i post my problem on the community.
you are very kind, polite and good! your response is very helpful to me!
本当にありがとうございます。熱心に勉強します。