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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3590 Questions
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  • Not Answered

    PGA970 with ARM Cortex M0 - Interrupts not working 0

    3275 views
    7 replies
    Latest over 3 years ago
    by PaulRo
  • Not Answered

    Does Cortex-M0+ has a flash patch mechanism similar to the FPB function of Cortex-M4? 0

    • Cortex-M0+
    3346 views
    2 replies
    Latest over 3 years ago
    by Serval
  • Not Answered

    Is there a way to generate PC sample packets and obtain the corresponding local timestamps by ITM in Cortex M4? 0

    • CoreSight Debug and Trace
    • Cortex-M4
    1131 views
    0 replies
    Started over 3 years ago
    by dddyyylll
  • Not Answered

    Will PL192 cancel an interrupt if VICSWPriorityMask bit set? 0

    1137 views
    1 reply
    Latest over 3 years ago
    by Jerry Fan
  • Not Answered

    How to use DWT mechanism of cortex-m33 to obtain the corresponding instruction and accessed memory in the run time? +1

    2077 views
    2 replies
    Latest over 3 years ago
    by support9
  • Not Answered

    Real differences between Cortex-R and M 0

    • Architecture
    • Cortex-R
    • Real-Time
    • Cortex-M
    4137 views
    1 reply
    Latest over 3 years ago
    by MRA_HRTS
  • Not Answered

    Texas Instruments BQ294682 chip: overvoltage protection circuit scheme for lithium batteries 0

    1320 views
    0 replies
    Started over 3 years ago
    by HaoQiCore Technology
  • Answered

    Detecting a pending interrupt before cpsie i instruction 0

    • Interrupt Handling
    • 5 (BusFault)
    2752 views
    3 replies
    Latest over 3 years ago
    by Krischu
  • Answered

    How to switch from JTAG to SWD? 0

    • JTAG
    • SWD
    2566 views
    2 replies
    Latest over 3 years ago
    by peterg12
  • Not Answered

    Best MCU(s) for ease of FDA verification / validation? 0

    • Microcontroller (MCU)
    1216 views
    0 replies
    Started over 3 years ago
    by AidanofVT
  • Answered

    cbnz - Error: branch out of range 0

    3169 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Suggested Answer

    memcpy on cortex-m7 causes unaligned usage fault 0

    • Cortex-M7
    • Memory Access Instructions
    3725 views
    3 replies
    Latest over 3 years ago
    by Pavel A
  • Not Answered

    RE: Testing contents of a memory cell for 0 0

    1185 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Answered

    Testing contents of a memory cell for 0 0

    • Arm Assembly Language (ASM)
    1520 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    PRIS and BFHFNMINS in AIRCR 0

    • TrustZone
    • Cortex-M33
    • Armv8-M
    1377 views
    0 replies
    Started over 3 years ago
    by Hsuan
  • Not Answered

    Hi ARM, clarify me, Who does the stacking and un-stacking in cortex m4 processor. who will take care process part in cortex m4 processor? 0

    876 views
    0 replies
    Started over 3 years ago
    by ARUNAKUMARA
  • Not Answered

    How to exit UsageFaultHandler() 0

    1104 views
    0 replies
    Started over 3 years ago
    by Yang Xie
  • Answered

    Aarch64 State of general purpose registers when exception is taken or returned. 0

    1577 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    ARM Cortex-A17 clock speed specification. 0

    • Arm Support
    1527 views
    0 replies
    Started over 3 years ago
    by Sjane
  • Suggested Answer

    TrustZone Address Space Controller with CHI interface 0

    • Platform Security Architecture (PSA)
    • AMBA 5 CHI
    • TrustZone Address Space Controllers
    • Trusted Execution Environment (TEE)
    • TrustZone
    2049 views
    1 reply
    Latest over 3 years ago
    by Josh8507
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