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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Answered

    GPT and Caching +1

    1855 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Cortex R5 vs R5F +1

    • Cortex-R5
    3714 views
    2 replies
    Latest over 3 years ago
    by Oliver Beirne Arm Employee Badge
  • Suggested Answer

    IRQ not firing when in SVC call 0

    • Interrupt Handling
    • AArch64
    1857 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    STM32F030K6T6TR Able to program 1st time 0

    • STM32 F0
    886 views
    0 replies
    Started over 3 years ago
    by MikeH32096
  • Not Answered

    PMU cyclic counter not updating for cortex r52 0

    1714 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Answered

    How the PE accesses peripherals registers and memories? 0

    • Peripheral Devices
    • SMMUv3
    2380 views
    3 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to distinguish B<c>.W and DSB commands in ARMv7M architecture +1

    2493 views
    2 replies
    Latest over 3 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Question about SMMU 0

    • SMMUv3
    1611 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Relationship between PSEL and PENABLE signals in the APB Protocol. 0

    • APB
    • Protocols
    • Bus Interface
    • AMBA 3 APB Interface
    • SoC Verification
    6236 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Linux on ARMv8 emulation under Foundation Platform doesn't work 0

    2444 views
    6 replies
    Latest over 3 years ago
    by Nicholas909
  • Not Answered

    How To perform system or software reset for CORTEX R5 from the software 0

    1461 views
    0 replies
    Started over 3 years ago
    by santhosh G n
  • Answered

    Does cortex R52 core support the "live watch" function during the Debug processing? +1

    2567 views
    2 replies
    Latest over 3 years ago
    by Stephen Theobald Arm Employee Badge
  • Suggested Answer

    Are there any practical differences between the Arm M0 and M3 for the C programmer? 0

    • Cortex-M0
    • Instruction Sets
    • Cortex-M3
    • GCC
    5473 views
    1 reply
    Latest over 3 years ago
    by WestfW
  • Not Answered

    LPC1850 with S25FL256 SPI FLash 0

    1072 views
    0 replies
    Started over 3 years ago
    by SantoshMengade
  • Not Answered

    cortex-R5 boot bare_metal code 0

    1009 views
    0 replies
    Started over 3 years ago
    by TTzhang
  • Not Answered

    Expected UART interrupt behavior on mps2_an521 0

    • Interrupt Handling
    • mps2
    1273 views
    0 replies
    Started over 3 years ago
    by SilentMike
  • Suggested Answer

    Can anyone help me to compile a modern kernel for the Psion 5MX? 0

    4284 views
    1 reply
    Latest over 3 years ago
    by Hemendra Arm Employee Badge
  • Not Answered

    Cortex-A53 in i.MX8M Mini - Bare Metal Programming 0

    1821 views
    0 replies
    Started over 3 years ago
    by Navaneethan
  • Not Answered

    Cortex-M1 Set Initial SP Value and the Reset Value 0

    • R15 (PC Program Counter)
    • R13 (SP Stack Pointer)
    • Cortex-M
    1603 views
    0 replies
    Started over 3 years ago
    by Julio Cesar Molina Saqui
  • Not Answered

    how to use LPC1857 on chip non continuous RAM in keil IDE 0

    1097 views
    0 replies
    Started over 3 years ago
    by SantoshMengade
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