STM32F103 - Switching from JTAG to SWD


I am working with an STM32 board, a JLink EDU and STM32Cude IDE and trying to understand the SWD protocol better. I am observing the SWD signals on an Oscilloscope and came across something that I cannot understand.

I have noticed the following phases during startup:

1) SWDIO goes HIGH for 50+ cycles

2) 0xE79E is sent

3) SWDIO goes HIGH for around 56 cycles

This is normal for what all the documentation I have found says.

After this I have a phase where the next 16 bits clocked in are "0110110110110111" (0xEDB6). Documentation on the Internet calls this the deprecated sequence. Does this mean that the JLink just sends both sequences to make sure that the SWJ-DP is definitely in SW-DP mode?

After this sequence, SWDIO goes HIGH again for 50+ cycles followed by 12+ Idle cycles and a READID command as mentioned in most References online.

My question is, is there a way to figure out when to use these deprecated sequences? Where can I find a full list of these sequences?

I will try debugging with an ST Link later to see if this behavior is related to the debugger or the IDE itself.