PMU cyclic counter not updating for cortex r52

I am using Cortex-r52 processor.

1.Enabling PMU user access - in the Performance Monitors User Enable Register (PMUSERENR), set the EN,bit[0] to 1.

__asm__ volatile (
"MRC p15, 0, r0, c9, c14, 0 \t\n"
"ORR r0, r0, #0x01\t\n"
"MCR p15, 0, r0, c9, c14, 0 \t\n"
"BX lr\t\n"
:
:

);

2.Enabling the PMU - in the Performance Monitors Control Register (PMCR), set the E,bit[0] to 1.

__asm__ volatile (
"MRC p15, 0, r0, c9, c12, 0\t\n"
"ORR r0, r0, #0x01 \t\n"
"MCR p15, 0, r0, c9, c12, 0 \t\n"
"BX lr\t\n"
:
:

);

3.Enabling the cycle counter (CCNT) - in the Performance Monitors Count Enable Set Register (PMCNTENSET), set the C,bit[31] to 1

__asm__ volatile (
"MOV r0, #0x80000000\t\n"
"MCR p15, 0, r0, c9, c12, 1\t\n"
"BX lr\t\n"
:
:

);

4. Resetting the cycle counter (CCNT) - in the Performance Monitors Control Register (PMCR), set the C,bit[2] to 1.

uint32_t value=0;
__asm__ volatile (
"MRC p15, 0, %[result], c9, c13, 0 \t\n"
"BX lr\t\n"
: [result] "=&r" (value)
:
);
return value;

5.Disabling the cycle counter (CCNT) - in the Performance Monitors Count Enable Clear Register (PMCNTENCLR), set the C,bit[31] to 1.

__asm__ volatile (
"MOV r0, #0x80000000\t\n"
"MCR p15, 0, r0, c9, c12, 2\t\n"
"BX lr\t\n"
:
:

);

6.Reading the value of the cycle counter (CCNT) - the value of the cycle counter is stored in the Performance Monitors Cycle Count Register (PMCCNTR). uint32_t value=0;
__asm__ volatile (
"MRC p15, 0, %[result], c9, c13, 0 \t\n"
"BX lr\t\n"
: [result] "=&r" (value)
:
);
return value;

I have done above steps to configure and read cyclic counter value, but I am getting 0 all the time.