Hi,
As per the title says, I'm getting an unaligned memory access fault with an STRH instruction. I know the memory referenced in the instruction is unaligned, but I only expected a performance penalty, not a hard fault. Instruction that causes the error:
strh r7, [r0, #4]
Register values:
Have added before/after register values for SCB.
Before:
Register Address ValueSystemControl 0xe000e000 SCB-ACTLR 0xe000e008 0x1000 SCB-CPUID 0xe000ed00 0x411fc271 SCB-ICSR 0xe000ed04 0xc81000VECTACTIVE [8:0] 0x0RETTOBASE [11] RETTOBASE_0VECTPENDING [20:12] 0x81ISRPENDING [22] ISRPENDING_1PENDSTCLR [25] PENDSTCLR_0PENDSTSET [26] PENDSTSET_0PENDSVCLR [27] PENDSVCLR_0PENDSVSET [28] PENDSVSET_0NMIPENDSET [31] NMIPENDSET_0SCB-VTOR 0xe000ed08 0x0 SCB-AIRCR 0xe000ed0c 0xfa050000 SCB-SCR 0xe000ed10 0x0 SCB-CCR 0xe000ed14 0x70200 SCB-SHPR1 0xe000ed18 0x0 SCB-SHPR2 0xe000ed1c 0x0 SCB-SHPR3 0xe000ed20 0xf0000000 SCB-SHCSR 0xe000ed24 0x10000 SCB-CFSR 0xe000ed28 0x0IACCVIOL [0] IACCVIOL_0DACCVIOL [1] DACCVIOL_0MUNSTKERR [3] MUNSTKERR_0MSTKERR [4] MSTKERR_0MLSPERR [5] MLSPERR_0MMARVALID [7] MMARVALID_0IBUSERR [8] IBUSERR_0PRECISERR [9] PRECISERR_0IMPRECISERR [10] IMPRECISERR_0UNSTKERR [11] UNSTKERR_0STKERR [12] STKERR_0LSPERR [13] LSPERR_0BFARVALID [15] BFARVALID_0UNDEFINSTR [16] UNDEFINSTR_0INVSTATE [17] INVSTATE_0INVPC [18] INVPC_0NOCP [19] NOCP_0UNALIGNED [24] UNALIGNED_0DIVBYZERO [25] DIVBYZERO_0SCB-HFSR 0xe000ed2c 0x0VECTTBL [1] VECTTBL_0FORCED [30] FORCED_0DEBUGEVT [31] DEBUGEVT_0SCB-DFSR 0xe000ed30 0x0 SCB-MMFAR 0xe000ed34 0x0 SCB-BFAR 0xe000ed38 0x0
After:
Register Address ValueSystemControl 0xe000e000 SCB-ACTLR 0xe000e008 0x1000 SCB-CPUID 0xe000ed00 0x411fc271 SCB-ICSR 0xe000ed04 0x481803 SCB-VTOR 0xe000ed08 0x0 SCB-AIRCR 0xe000ed0c 0xfa050000 SCB-SCR 0xe000ed10 0x0 SCB-CCR 0xe000ed14 0x70200 SCB-SHPR1 0xe000ed18 0x0 SCB-SHPR2 0xe000ed1c 0x0 SCB-SHPR3 0xe000ed20 0xf0000000 SCB-SHCSR 0xe000ed24 0x10000 SCB-CFSR 0xe000ed28 0x1000000IACCVIOL [0] IACCVIOL_0DACCVIOL [1] DACCVIOL_0MUNSTKERR [3] MUNSTKERR_0MSTKERR [4] MSTKERR_0MLSPERR [5] MLSPERR_0MMARVALID [7] MMARVALID_0IBUSERR [8] IBUSERR_0PRECISERR [9] PRECISERR_0IMPRECISERR [10] IMPRECISERR_0UNSTKERR [11] UNSTKERR_0STKERR [12] STKERR_0LSPERR [13] LSPERR_0BFARVALID [15] BFARVALID_0UNDEFINSTR [16] UNDEFINSTR_0INVSTATE [17] INVSTATE_0INVPC [18] INVPC_0NOCP [19] NOCP_0UNALIGNED [24] UNALIGNED_1DIVBYZERO [25] DIVBYZERO_0SCB-HFSR 0xe000ed2c 0x40000000VECTTBL [1] VECTTBL_0FORCED [30] FORCED_1DEBUGEVT [31] DEBUGEVT_0SCB-DFSR 0xe000ed30 0x0 SCB-MMFAR 0xe000ed34 0x0 SCB-BFAR 0xe000ed38 0x0
What have you got in CCR? It's got a config bit:
UNALIGN_TRP, bit[3]
Controls the trapping of unaligned word or halfword accesses:
0 Trapping disabled.
1 Trapping enabled.
Unaligned load-store multiples and word or halfword exclusive accesses always fault.
Thanks for the suggestion. That bit is already set to 0, was one of the first things I checked.
Is there any chance that NXP didn't implement the support for unaligned memory access, as described in the Cortex-M7 ARM reference manual?