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Unaligned memory access fault with STRH on Cortex-M7

Hi,

As per the title says, I'm getting an unaligned memory access fault with an STRH instruction. I know the memory referenced in the instruction is unaligned, but I only expected a performance penalty, not a hard fault.  Instruction that causes the error:

strh    r7, [r0, #4]

Register values:

Have added before/after register values for SCB.

  • Before:

    Register Address Value
    SystemControl 0xe000e000
    SCB-ACTLR 0xe000e008 0x1000

    SCB-CPUID 0xe000ed00 0x411fc271

    SCB-ICSR 0xe000ed04 0xc81000
    VECTACTIVE [8:0] 0x0
    RETTOBASE [11] RETTOBASE_0
    VECTPENDING [20:12] 0x81
    ISRPENDING [22] ISRPENDING_1
    PENDSTCLR [25] PENDSTCLR_0
    PENDSTSET [26] PENDSTSET_0
    PENDSVCLR [27] PENDSVCLR_0
    PENDSVSET [28] PENDSVSET_0
    NMIPENDSET [31] NMIPENDSET_0
    SCB-VTOR 0xe000ed08 0x0

    SCB-AIRCR 0xe000ed0c 0xfa050000

    SCB-SCR 0xe000ed10 0x0

    SCB-CCR 0xe000ed14 0x70200

    SCB-SHPR1 0xe000ed18 0x0

    SCB-SHPR2 0xe000ed1c 0x0

    SCB-SHPR3 0xe000ed20 0xf0000000

    SCB-SHCSR 0xe000ed24 0x10000

    SCB-CFSR 0xe000ed28 0x0
    IACCVIOL [0] IACCVIOL_0
    DACCVIOL [1] DACCVIOL_0
    MUNSTKERR [3] MUNSTKERR_0
    MSTKERR [4] MSTKERR_0
    MLSPERR [5] MLSPERR_0
    MMARVALID [7] MMARVALID_0
    IBUSERR [8] IBUSERR_0
    PRECISERR [9] PRECISERR_0
    IMPRECISERR [10] IMPRECISERR_0
    UNSTKERR [11] UNSTKERR_0
    STKERR [12] STKERR_0
    LSPERR [13] LSPERR_0
    BFARVALID [15] BFARVALID_0
    UNDEFINSTR [16] UNDEFINSTR_0
    INVSTATE [17] INVSTATE_0
    INVPC [18] INVPC_0
    NOCP [19] NOCP_0
    UNALIGNED [24] UNALIGNED_0
    DIVBYZERO [25] DIVBYZERO_0
    SCB-HFSR 0xe000ed2c 0x0
    VECTTBL [1] VECTTBL_0
    FORCED [30] FORCED_0
    DEBUGEVT [31] DEBUGEVT_0
    SCB-DFSR 0xe000ed30 0x0

    SCB-MMFAR 0xe000ed34 0x0

    SCB-BFAR 0xe000ed38 0x0

  • After:

    Register Address Value
    SystemControl 0xe000e000
    SCB-ACTLR 0xe000e008 0x1000

    SCB-CPUID 0xe000ed00 0x411fc271

    SCB-ICSR 0xe000ed04 0x481803

    SCB-VTOR 0xe000ed08 0x0

    SCB-AIRCR 0xe000ed0c 0xfa050000

    SCB-SCR 0xe000ed10 0x0

    SCB-CCR 0xe000ed14 0x70200

    SCB-SHPR1 0xe000ed18 0x0

    SCB-SHPR2 0xe000ed1c 0x0

    SCB-SHPR3 0xe000ed20 0xf0000000

    SCB-SHCSR 0xe000ed24 0x10000

    SCB-CFSR 0xe000ed28 0x1000000
    IACCVIOL [0] IACCVIOL_0
    DACCVIOL [1] DACCVIOL_0
    MUNSTKERR [3] MUNSTKERR_0
    MSTKERR [4] MSTKERR_0
    MLSPERR [5] MLSPERR_0
    MMARVALID [7] MMARVALID_0
    IBUSERR [8] IBUSERR_0
    PRECISERR [9] PRECISERR_0
    IMPRECISERR [10] IMPRECISERR_0
    UNSTKERR [11] UNSTKERR_0
    STKERR [12] STKERR_0
    LSPERR [13] LSPERR_0
    BFARVALID [15] BFARVALID_0
    UNDEFINSTR [16] UNDEFINSTR_0
    INVSTATE [17] INVSTATE_0
    INVPC [18] INVPC_0
    NOCP [19] NOCP_0
    UNALIGNED [24] UNALIGNED_1
    DIVBYZERO [25] DIVBYZERO_0
    SCB-HFSR 0xe000ed2c 0x40000000
    VECTTBL [1] VECTTBL_0
    FORCED [30] FORCED_1
    DEBUGEVT [31] DEBUGEVT_0
    SCB-DFSR 0xe000ed30 0x0

    SCB-MMFAR 0xe000ed34 0x0

    SCB-BFAR 0xe000ed38 0x0

  • What have you got in CCR?  It's got a config bit:

    UNALIGN_TRP, bit[3]

    Controls the trapping of unaligned word or halfword accesses:

    1. 0  Trapping disabled.

    2. 1  Trapping enabled.

    Unaligned load-store multiples and word or halfword exclusive accesses always fault.

  • Is there any chance that NXP didn't implement the support for unaligned memory access, as described in the Cortex-M7 ARM reference manual?