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SoC Design forum
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SoC Design forum
  • Description The SoC Design community is the place to be when planning, designing, or researching your SoC. Here, we discuss design and implementation, Artisan or other physical IP, manufacturing processes and technology challenges.
  • Threads 321 Questions
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Unanswered questions
  • Ravi V.
    AXI4 transaction attributes
    Not Answered 6 days ago
  • IPDeveloper
    AMBA 5 CHI Link Layer (L-Credit Return)
    Suggested Answer 1 month ago
  • zhibo05
    Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?
    Answered 8 days ago
  • ISHWAR GANIGER
    BUSY transfer just before the last transfer in a burst by a AHB Master.
    Not Answered 27 days ago
  • Sreekanth Reddy
    AMBA AXI reset
    Not Answered over 1 year ago
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  • Not Answered

    AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0

    6439 views
    1 reply
    Latest 6 months ago
    by guimers8
  • Not Answered

    Missing CoreSight components in /renensas/r8a77970.dtsi 0

    • CoreSight Trace Funnel
    • replicator
    • TPIU
    • AMBA 3 ATB Interface
    • CoreSight System Trace Macrocell (STM)
    5805 views
    0 replies
    Started 6 months ago
    by LWT
  • Not Answered

    simple design verilog code 0

    5953 views
    0 replies
    Started 6 months ago
    by legend137
  • Answered

    WSTRB calculation 0

    7222 views
    2 replies
    Latest 6 months ago
    by Ravi V.
  • Answered

    Handshaking for the write data channel 0

    7399 views
    3 replies
    Latest 7 months ago
    by Colin Campbell
  • Not Answered

    Looking for manufacturer to produce our motherboard design 0

    5838 views
    0 replies
    Started 7 months ago
    by Fran Saez
  • Not Answered

    AXI3 locked access +1

    • AMBA
    • AXI
    9491 views
    3 replies
    Latest 7 months ago
    by Colin Campbell
  • Answered

    Difference btw AXI3 and AXI4 0

    • AMBA
    • AXI3
    • AXI4
    • Interface
    20219 views
    6 replies
    Latest 7 months ago
    by Colin Campbell
  • Answered

    WID not present in AXI4 0

    6596 views
    1 reply
    Latest 7 months ago
    by Colin Campbell
  • Answered

    FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0

    6459 views
    1 reply
    Latest 7 months ago
    by Colin Campbell
  • Answered

    Handling invalid AXI address requests 0

    • AXI4-Lite
    • Cortex-M System Design Kit
    • Cortex-M
    7179 views
    1 reply
    Latest 7 months ago
    by Colin Campbell
  • Answered

    AXI INC type transfer 0

    6798 views
    2 replies
    Latest 7 months ago
    by Ravi V.
  • Answered

    Question about AXI4 WLAST 0

    6956 views
    1 reply
    Latest 7 months ago
    by Colin Campbell
  • Not Answered

    AMBA AHB Lite addressable space for byte size transfer 0

    • AMBA AHB Controllers
    10717 views
    3 replies
    Latest 7 months ago
    by DonVerilog
  • Answered

    AXI4:- Unaligned transfer 0

    8658 views
    3 replies
    Latest 8 months ago
    by Colin Campbell
  • Answered

    About AXI protocol Specification 0

    7503 views
    1 reply
    Latest 8 months ago
    by Colin Campbell
  • Answered

    AXI3 WRAP burst 0

    7527 views
    1 reply
    Latest 8 months ago
    by Colin Campbell
  • Not Answered

    NIC301 sizing 0

    7564 views
    1 reply
    Latest 8 months ago
    by Colin Campbell
  • Answered

    AXI3 write response dependencies 0

    7967 views
    1 reply
    Latest 8 months ago
    by Colin Campbell
  • Answered

    AXI Read Transaction Dependencies 0

    8033 views
    1 reply
    Latest 8 months ago
    by Colin Campbell
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