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SoC Design forum
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SoC Design forum
  • Description The SoC Design community is the place to be when planning, designing, or researching your SoC. Here, we discuss design and implementation, Artisan or other physical IP, manufacturing processes and technology challenges.
  • Threads 321 Questions
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Unanswered questions
  • Ravi V.
    AXI4 transaction attributes
    Not Answered 6 days ago
  • IPDeveloper
    AMBA 5 CHI Link Layer (L-Credit Return)
    Suggested Answer 1 month ago
  • zhibo05
    Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?
    Answered 8 days ago
  • ISHWAR GANIGER
    BUSY transfer just before the last transfer in a burst by a AHB Master.
    Not Answered 27 days ago
  • Sreekanth Reddy
    AMBA AXI reset
    Not Answered over 1 year ago
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  • Not Answered

    Multicore Debug SW/Jtag IP +2

    9417 views
    3 replies
    Latest 1 month ago
    by Andy Neil
  • Answered

    AMBA APB 0

    • APB
    2532 views
    5 replies
    Latest 1 month ago
    by Andy Neil
  • Not Answered

    AMBA 0

    • AMBA
    1965 views
    1 reply
    Latest 1 month ago
    by Colin Campbell
  • Not Answered

    In AXI Why there is a read response in each data transfer? 0

    1861 views
    1 reply
    Latest 1 month ago
    by Colin Campbell
  • Not Answered

    AMBA APB +1

    • APB
    1896 views
    1 reply
    Latest 1 month ago
    by Colin Campbell
  • Answered

    AMBA APB 0

    2317 views
    3 replies
    Latest 1 month ago
    by Colin Campbell
  • Not Answered

    ARM CHI Issue C Specification - Can we receive DataSepResp, RespSepData in any order at a CHI Requester Node? 0

    • SoC Designer
    • AMBA 5 CHI
    • Cache Coherent Interconnect
    1733 views
    0 replies
    Started 1 month ago
    by Jalaj29
  • Not Answered

    AXI4 Bus Bandwidth/Data Transfer increase 0

    • AXI
    • AXI4
    • Bus Architecture
    • Hardware Modelling/Simulation
    2907 views
    2 replies
    Latest 2 months ago
    by willo144
  • Not Answered

    Conversions without printf 0

    2878 views
    1 reply
    Latest 2 months ago
    by Andy Neil
  • Not Answered

    DesignStart software related question 0

    • DesignStart
    2861 views
    0 replies
    Started 2 months ago
    by Mcgiwer
  • Suggested Answer

    outsanading behaviour in AXI Vs memory latency 0

    • AMBA 4
    • AMBA 3 AXI Interface
    4135 views
    3 replies
    Latest 2 months ago
    by Christopher Tory
  • Not Answered

    CCN-502 profiling: how do I know which port HN-F is attached to? 0

    3221 views
    0 replies
    Started 2 months ago
    by Oscar Huang
  • Answered

    ARM AMBA AXI4 read channel information 0

    • AXI4
    4321 views
    1 reply
    Latest 2 months ago
    by Colin Campbell
  • Answered

    outstanding transaction in AXI4 protocol 0

    11817 views
    4 replies
    Latest 3 months ago
    by Colin Campbell
  • Not Answered

    Help with AXI4 payload with data bus width of 32 bits 0

    • AXI4
    4472 views
    1 reply
    Latest 3 months ago
    by Colin Campbell
  • Not Answered

    AMBA 5 CHI Streaming ordered WriteUnique Txn 0

    • AMBA 5 CHI
    6357 views
    1 reply
    Latest 3 months ago
    by Francis Fang
  • Answered

    Atomic access LDR/STR vs LDREX/STREX 0

    • AHB-Lite
    • DesignStart
    8927 views
    3 replies
    Latest 3 months ago
    by Jenkins
  • Not Answered

    Need advice on finding "low end" SoC with Android support 0

    4586 views
    2 replies
    Latest 3 months ago
    by Andy Victors
  • Not Answered

    Best most recent text on ARM arch 0

    6121 views
    2 replies
    Latest 3 months ago
    by d.ry
  • Suggested Answer

    TRACE Signal usage in AXI5, ACE5, ACE5-lite 0

    4755 views
    1 reply
    Latest 3 months ago
    by Xingguang Feng
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