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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 735 Questions
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  • Answered

    How to benchmark code on FVP_MPS2_Cortex-M4 simulator? +1

    • CMSIS
    8584 views
    14 replies
    Latest over 3 years ago
    by DavidAl
  • Answered

    Startup code for FVP_MPS2_Cortex-M4 simulator? 0

    2390 views
    1 reply
    Latest over 3 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Which GIC does Armv-A Base RevC AEM FVP implement? 0

    • GICv3/v4
    • Fixed Virtual Platforms (FVPs)
    2645 views
    1 reply
    Latest over 3 years ago
    by a.surati
  • Answered

    Sram compiler installation problem +1

    • SRAM
    • SRAM Memory
    • Compilers
    2565 views
    2 replies
    Latest over 3 years ago
    by JINSUKLEE
  • Suggested Answer

    Watch Dog Timer 0

    3017 views
    1 reply
    Latest over 3 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Is DAP-LITE enough for the debug of Cortex-A7? 0

    • CoreSight DAP-Lite
    2736 views
    2 replies
    Latest over 3 years ago
    by asic_xuan
  • Answered

    Does tlm_quantumkeeper::set_global_quantum affect Fast Models? 0

    3278 views
    2 replies
    Latest over 3 years ago
    by Oscar Huang
  • Not Answered

    Model for GIC-625 0

    1063 views
    0 replies
    Started over 3 years ago
    by Oscar Huang
  • Not Answered

    Using Tmax Tetramax models for memories for scan vector generation. 0

    3293 views
    2 replies
    Latest over 4 years ago
    by Jeff_from_Draper
  • Answered

    Is Cortex-R82 fast model available? 0

    4790 views
    3 replies
    Latest over 4 years ago
    by Daniel Owens Arm Employee Badge
  • Not Answered

    Has anyone ever generated bin file for CXDT? 0

    12236 views
    1 reply
    Latest over 4 years ago
    by ghan
  • Not Answered

    Nic-400 read and write acceptance/issue configuration in socrates 0

    • socrates
    • CoreLink NIC-400
    1858 views
    0 replies
    Started over 4 years ago
    by vrk21
  • Not Answered

    How can I fix timing violation in NIC-400 bus matrix? 0

    • CoreLink NIC-400
    • CoreLink NIC-400 Network Interconnect
    1415 views
    0 replies
    Started over 4 years ago
    by Watech2010
  • Not Answered

    Regarding USB3.X Interface in ARM based microcontrollers 0

    18137 views
    1 reply
    Latest over 4 years ago
    by mkleox
  • Answered

    Should the Data value be 0 when corresponding BE is 0 in Arm CHI E Spec? 0

    • AMBA 5 CHI
    2404 views
    1 reply
    Latest over 4 years ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    In CHI, is "Device" memory type transaction, a way, to implement narrow Read transfer's ? 0

    • AMBA 5 CHI
    • CHI
    1412 views
    0 replies
    Started over 4 years ago
    by Neel_chi
  • Not Answered

    CHI data packet values for those packets outside valid byte window in a Device memory type txn 0

    1091 views
    0 replies
    Started over 4 years ago
    by Neel_chi
  • Not Answered

    CHI Device memory type unaligned transactions when size exceeds beyond next size boundary 0

    • AMBA 5 CHI
    • CHI
    1413 views
    0 replies
    Started over 4 years ago
    by Neel_chi
  • Not Answered

    CHI data size for each packets based on data bus width's 0

    • AMBA 5 CHI
    • CHI
    1629 views
    0 replies
    Started over 4 years ago
    by Neel_chi
  • Not Answered

    How to connect Master AHB lite to AHB5 Slave 0

    2268 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
<>
Topics being discussed in this forum
  • ACE
  • AEMv8 FVP
  • AHB
  • AHB5
  • AHB-Lite
  • AMBA
  • AMBA 5
  • AMBA 5 CHI
  • APB
  • Arm Development Studio
  • Armv8-M
  • AXI
  • AXI4
  • Bus Architecture
  • CHI
  • CoreLink NIC-400 Network Interconnect
  • CoreSight
  • Cortex-A
  • Cortex-M
  • DesignStart
  • Fast Models
  • Fixed Virtual Platforms (FVPs)
  • Interface
  • socrates
  • TrustZone