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How to connect Master AHB lite to AHB5 Slave

Hai Nguyen

Hi everyone, I have a problem when I connect master AHB lite to AHB5 Slave. Because I want to bring AHB5_AXI5_bridge for test on FPGA. I connect master AHB lite to slave AHB5 and Master AXI5 to AXI4 of Bram controller. As you know AHB5 and AXI5 are different between AHB lite and AXI4 that reason some signals of AHB5 and AXI5 are residual, which signals I don't do anything.  Maybe I have some wrong that why you can see the address of ahb5_axi5_bridge(xhb500_ahb_to_axi_br_0) separate with MicroBlaze. Due to I want to test read/write when using AHB5_AXI5_bridge, if as the address off ahb5_axi5_bridge separate with MicroBlaze so I can not use C code send data through ahb5_axi5_brigde. 


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    My first thought is that this looks like an issue with the MicroBlaze platform use, and not something I can help with (me not having any MicroBlaze experience), and I'd guess that is certainly the case for the question about addressing.

    For the AHB-lite to AHB5 connection question, AHB5 is just AHB-lite with some optional additional signals, so if you are not using the added AHB5 functionality it should be a simple case of tying off the unused bridge inputs and ignoring the unused outputs.

    AHB-lite has no concepts of "security" or "exclusive transfers", so the AHB5 HNONSEC input on the XHB-500 bridge can be tied off to 1'b1 (to avoid restricting access to secure areas of the AHB5 or AXI domains), and the AHB5 HEXCL input tied low (as we will not be signaling "exclusive" transfers. HMASTER is used to indicate the "exclusive" thread number, so again as it is unused here it can be tied off to any static value. HEXOKAY left unconnected.

    For the XHB-500 HQOS, HREGION and HNSAID inputs, these are not AHB5 signals, so are just unofficial address phase timed "sideband" signals. These are all passed through the XHB-500 bridge to similarly named AXI5 ports, none of which are supported by the AXI4 protocol, so will presumably be ignored when you connect to the AXI4 BRAM target. So I'd suggest just tying all these AHB5 "sideband" inputs to 4'b0000.

    But probably better asked on a MicroBlaze support forum instead of here.

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  • 0

    My first thought is that this looks like an issue with the MicroBlaze platform use, and not something I can help with (me not having any MicroBlaze experience), and I'd guess that is certainly the case for the question about addressing.

    For the AHB-lite to AHB5 connection question, AHB5 is just AHB-lite with some optional additional signals, so if you are not using the added AHB5 functionality it should be a simple case of tying off the unused bridge inputs and ignoring the unused outputs.

    AHB-lite has no concepts of "security" or "exclusive transfers", so the AHB5 HNONSEC input on the XHB-500 bridge can be tied off to 1'b1 (to avoid restricting access to secure areas of the AHB5 or AXI domains), and the AHB5 HEXCL input tied low (as we will not be signaling "exclusive" transfers. HMASTER is used to indicate the "exclusive" thread number, so again as it is unused here it can be tied off to any static value. HEXOKAY left unconnected.

    For the XHB-500 HQOS, HREGION and HNSAID inputs, these are not AHB5 signals, so are just unofficial address phase timed "sideband" signals. These are all passed through the XHB-500 bridge to similarly named AXI5 ports, none of which are supported by the AXI4 protocol, so will presumably be ignored when you connect to the AXI4 BRAM target. So I'd suggest just tying all these AHB5 "sideband" inputs to 4'b0000.

    But probably better asked on a MicroBlaze support forum instead of here.

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