Hi everyone, I have a problem when I connect master AHB lite to AHB5 Slave. Because I want to bring AHB5_AXI5_bridge for test on FPGA. I connect master AHB lite to slave AHB5 and Master AXI5 to AXI4 of Bram controller. As you know AHB5 and AXI5 are different between AHB lite and AXI4 that reason some signals of AHB5 and AXI5 are residual, which signals I don't do anything. Maybe I have some wrong that why you can see the address of ahb5_axi5_bridge(xhb500_ahb_to_axi_br_0) separate with MicroBlaze. Due to I want to test read/write when using AHB5_AXI5_bridge, if as the address off ahb5_axi5_bridge separate with MicroBlaze so I can not use C code send data through ahb5_axi5_brigde.