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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Answered

    Working frequency on AMBA- APB,AHB, AXI +2

    • APB
    • AMBA
    • AXI
    • AHB
    • Interface
    18289 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ? +1

    • APB
    • AMBA
    16340 views
    4 replies
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    RMW operation on SRAM via AXI +1

    • AMBA
    • AXI
    • SRAM
    7234 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI narrow read with unaligned address 0

    • AMBA
    • AXI
    9724 views
    2 replies
    Latest over 8 years ago
    by jduarte
  • Not Answered

    AXI 0

    • AMBA
    • AXI
    • Interface
    6293 views
    3 replies
    Latest over 8 years ago
    by Simone Secchi
  • Answered

    AXI read transfer +1

    • AMBA
    • ACE
    • AXI
    • Interface
    9792 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    read transfers 0

    • AMBA
    • AXI
    • Interface
    4116 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    AXI +1

    • AMBA
    • AXI
    • amba4
    • Interface
    5766 views
    2 replies
    Latest over 8 years ago
    by Muthuvenkatesh
  • Answered

    GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER +1

    • CoreLink System Controllers
    • CoreLink GIC-500 Generic Interrupt Controller
    8818 views
    4 replies
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    GIC500 :: Not able to disable Affinity Routing +1

    • CoreLink System Controllers
    • Corelink
    • CoreLink GIC-500 Generic Interrupt Controller
    5220 views
    2 replies
    Latest over 8 years ago
    by danish259
  • Answered

    GIC 500 :: Not able to find the definition for GICD_IROUTERn register +1

    • CoreLink System Controllers
    • Corelink
    • CoreLink GIC-500 Generic Interrupt Controller
    5317 views
    2 replies
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail? +1

    • AMBA
    • AXI
    • Interface
    5726 views
    2 replies
    Latest over 8 years ago
    by bander
  • Not Answered

    Licensing FVP models 0

    • Arm Development Studio
    • Arm Compiler 6
    • Arm Cortex-R
    • Fixed Virtual Platforms
    • compiler
    • Arm Compiler
    4221 views
    1 reply
    Latest over 8 years ago
    by Mervyn Arm Employee Badge
  • Not Answered

    STM(System Trace Macrocell) 0

    • AMBA
    • AXI
    • system trace macrocell
    • Bus Architecture
    7949 views
    5 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Why does AHB or APB support only 16 slave devices? +1

    • APB
    • AMBA
    • AXI
    • AHB
    • Interface
    12289 views
    4 replies
    Latest over 8 years ago
    by Ravindran
  • Not Answered

    Why the address boundary for AHB burst should not cross 1KB 0

    • AMBA
    • AHB
    13692 views
    1 reply
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    why there is no split or retry responce in AXI ? +1

    • AMBA
    • AXI
    • AHB
    9316 views
    2 replies
    Latest over 9 years ago
    by Jay Zhao
  • Not Answered

    In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst? 0

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    6929 views
    3 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AHB HREADY low not after address phase +1

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    5757 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response? 0

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    15422 views
    9 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
<>
Topics being discussed in this forum
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  • AMBA 5 CHI
  • APB
  • Arm Development Studio
  • Armv8-M
  • AXI
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  • CoreLink NIC-400 Network Interconnect
  • CoreSight
  • Cortex-A
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  • Interface
  • socrates
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