PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.
APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles of an APB transfer internally by both Master and Slave.
You could design an APB slave that didn't need a PENABLE input as you describe. It would need a simple state machine to track the "idle", "setup" and "access" phases of each transfer. When PSEL is first sampled high on a PCLK rising edge this is the single cycle "setup" phase of a transfer when PREADY is "undefined", and then on each subsequent PCLK rising edge you would test PREADY to detect the end of the "access" phase of the transfer. The peripheral can then use the detected "setup" and "access" phases to know when to sample the PADDR/PWRITE timed control signals, and when to drive or sample PWDATA/PRDATA. If PSEL is next sampled low, the state machine moves into the "idle" state, but if PSEL is still sampled high the state machine moves back into the single cycle "setup" phase again for a back to back sequence of transfers. PENABLE must still be generated by the APB master so that simpler APB peripheral designs can just detect the "setup" and "access" phases of each transfer by gating together PSEL, PENABLE and PREADY. So you have two choices how to design the APB slave, either using PENABLE or by implementing a simple state machine.