hi, experts:
以Cortex-A7 CPU为例：
如果在程序执行过程中：发生了一个Asynchrous External Data Abort，它会很快进入Data Abort handler吗？
(Synchrous Data Abort会立即进入Data Abort handler.)
不清楚Asynchrous external data abort，什么时候才会进入Data abort handler!
best wishes,
hi,
应该是很快就进入Data Abort handler的，
所谓ansynchrous 是指和当前执行的指令没有关系，例如一个写已经写到buffer里面了，对于cpu来讲已经完成了，但是后来从buffer里往downstream写的时候出错了，这个就是async的data abort了。
如果是读，cpu的load指令会一直hold在那里，直到数据回来，这个时候的出错就是sync的abort了，因为cpu知道哪个指令错了。
所有的中断处理都是要求及时处理的，至于在哪个cycle进入handler，取决于cpu的microarchi和cpu所处的状态，例如在关中断时就需要等着。
async和sync的一个区别在于ln寄存器记录的值是否是handler处理完之后可以恢复执行的点。
hi, yongfeng:
假定发生Data Abort时，
DFSR ： 0x1C06
DFAR : 0x86f85800
根据DFSR的定义，可知：
ExT=1 ：表示发生了AXI Slave Error而不是Decode Error
WnR=1，表示为写操作
FS=0x16，表示Abort Type为Asynchrous External Data Abort
表明在对一个slave device做write操作时，发生了Asynchrous Data Abort?
此时DFAR是没有意义的吧？！
从上述2个register，还能得出什么有价值的debug info？
是的，应该很快的，类似中断，ARMv7手册上的描述如下：
A Data Abort exception can be generated by:
• A synchronous abort on a data read or write memory access. Exception entry is synchronous to the
instruction that generated the memory access.
• An asynchronous abort. The memory access that caused the abort can be any of:
— a data read or write access
— an instruction fetch or prefetch
— in a VMSA memory system, a translation table access.
Exception entry occurs asynchronously. It is similar to an interrupt, but uses either Abort mode or
Monitor mode, and the associated banked registers. Setting the CPSR.A bit prevents asynchronous
aborts from occurring.
There are no asynchronous internal aborts in ARMv7 and earlier architecture versions, so
asynchronous aborts are always asynchronous external aborts.
你的理解是正确的，
DFAR信息不够准确
对于Asynchrous External Data Abort：没有precise / imprecise之分吧。
只有Instruction prefetch abort ：才会有precise/imprecise之分？
Hi chinatiger,
你可以参考Cortex-A7 TRM:
7.4.1 External aborts handling
...
All store accesses to Device, Strongly-ordered, or inner and outer Non-cacheable normal
memory use the asynchronous abort mechanism, except for STREX, STREXB, STREXH, and
STREXD.
All store accesses to normal memory that is either inner cacheable or outer cacheable and
any evictions from L1 or L2 cache do not cause an abort in the processor, instead they
assert the nAXIERRIRQ pin. This is because the access that aborts might not relate
directly back to a specific processor in the cluster.
[注释] 以上内容只是针对Cortex-A7的。
hi Tiger,
arm arch 没有规定如何区分async abort是precise或者是imprecise，这个要看具体cpu类型，
以A7为例的话，我只找到一处是precise abort的：
"Load-Exclusive instructions take a precise abort if the memory attributes are:..."。
可以参考这个地方：
http://arminfo.emea.arm.com/help/index.jsp?topic=/com.arm.doc.den0013d/CHDEBCJI.html
对于Cortex-A8 : 判断precise / imprecise，只能通过IFSR，因此：我推测只能Instruction prefetch abort才会产生precise / imprecise
对于Cortex-A7 : IFSR确实没有定义相关bit用于判断precise / imprecise.
之前大牛的回复，可参考：
Simply, a "precise" data abort is one for which it is possible to identify unambiguously the instruction which caused the aborting memory access. Correspondingly, an "imprecise" data abort is the opposite i.e. a data abort for which it is not possible to identify the instruction which caused the aborting access.
An example of an imprecise data abort might be a data write which goes through a write buffer. In such a case, the eventual write to memory may come many cycles after the STR instruction which placed the data in the write buffer. In this situation, it is not generally possible to work backwards to identity the instruction.
Another example would be a cache cast-out of dirty data. Again, if this causes an abort then it is not possible to identify the instruction which modified the data in t he cache at some previous time.
Precise/Imprecise data abort in arm processor
A precise memory error is one where the core knows which instruction caused the fault. This can correspond to a load or a store accessing memory which does not exist, or a prefetch error where the address where an instruction is supposed to be does not exist.
Imprecise errors are caused by things such as cache line flushes hitting non-existent memory in cached cores. The data may have been in cache for some time, so the core does not know which instruction wrote the data which caused the error.
Re: Precise Memory Error
>对于Cortex-A8 : 判断precise / imprecise，只能通过IFSR，因此：我推测只能Instruction prefetch abort才会产生precise / imprecise
IFSR = Instruction Fault Status Register
The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last instruction fault.
Cortex-A8 TRM里面，关于IFSR的定义并没有precise / imprecise的信息。如下图：
也许你指的是 DFSR (Data Fault Status Register) ?
hi, Xingguang:
these bits definitions are related to precise/imprecise in IFSR:
bx01100 L1 translation, precise external abort etc
>these bits definitions are related to precise/imprecise in IFSR:
>bx01100 L1 translation, precise external abort etc
谢谢你的update！
IFSR 记录的是 instruction fetch相关的abort status。
Instruction fetch 产生的abort总是precise的。