hi, experts:
以Cortex-A7 CPU为例：
如果在程序执行过程中：发生了一个Asynchrous External Data Abort，它会很快进入Data Abort handler吗？
(Synchrous Data Abort会立即进入Data Abort handler.)
不清楚Asynchrous external data abort，什么时候才会进入Data abort handler!
best wishes,
hi, yongfeng:
对于Asynchrous External Data Abort：没有precise / imprecise之分吧。
只有Instruction prefetch abort ：才会有precise/imprecise之分？
hi Tiger,
arm arch 没有规定如何区分async abort是precise或者是imprecise，这个要看具体cpu类型，
以A7为例的话，我只找到一处是precise abort的：
"Load-Exclusive instructions take a precise abort if the memory attributes are:..."。
可以参考这个地方：
http://arminfo.emea.arm.com/help/index.jsp?topic=/com.arm.doc.den0013d/CHDEBCJI.html
对于Cortex-A8 : 判断precise / imprecise，只能通过IFSR，因此：我推测只能Instruction prefetch abort才会产生precise / imprecise
对于Cortex-A7 : IFSR确实没有定义相关bit用于判断precise / imprecise.
之前大牛的回复，可参考：
Simply, a "precise" data abort is one for which it is possible to identify unambiguously the instruction which caused the aborting memory access. Correspondingly, an "imprecise" data abort is the opposite i.e. a data abort for which it is not possible to identify the instruction which caused the aborting access.
An example of an imprecise data abort might be a data write which goes through a write buffer. In such a case, the eventual write to memory may come many cycles after the STR instruction which placed the data in the write buffer. In this situation, it is not generally possible to work backwards to identity the instruction.
Another example would be a cache cast-out of dirty data. Again, if this causes an abort then it is not possible to identify the instruction which modified the data in t he cache at some previous time.
Precise/Imprecise data abort in arm processor
A precise memory error is one where the core knows which instruction caused the fault. This can correspond to a load or a store accessing memory which does not exist, or a prefetch error where the address where an instruction is supposed to be does not exist.
Imprecise errors are caused by things such as cache line flushes hitting non-existent memory in cached cores. The data may have been in cache for some time, so the core does not know which instruction wrote the data which caused the error.
Re: Precise Memory Error
Hi chinatiger,
>对于Cortex-A8 : 判断precise / imprecise，只能通过IFSR，因此：我推测只能Instruction prefetch abort才会产生precise / imprecise
IFSR = Instruction Fault Status Register
The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last instruction fault.
Cortex-A8 TRM里面，关于IFSR的定义并没有precise / imprecise的信息。如下图：
也许你指的是 DFSR (Data Fault Status Register) ?
hi, Xingguang:
these bits definitions are related to precise/imprecise in IFSR:
bx01100 L1 translation, precise external abort etc
>these bits definitions are related to precise/imprecise in IFSR:
>bx01100 L1 translation, precise external abort etc
谢谢你的update！
IFSR 记录的是 instruction fetch相关的abort status。
Instruction fetch 产生的abort总是precise的。