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Asynchrous External Data Abort in ARMv7

hi, experts:

以Cortex-A7 CPU为例:

如果在程序执行过程中:发生了一个Asynchrous External Data Abort,它会很快进入Data Abort handler吗?

(Synchrous Data Abort会立即进入Data Abort handler.)

不清楚Asynchrous external data abort,什么时候才会进入Data abort handler!

best wishes,

Parents
  • Hi chinatiger,

    你可以参考Cortex-A7 TRM:

    7.4.1 External aborts handling

    ...

    ...

    All store accesses to Device, Strongly-ordered, or inner and outer Non-cacheable normal

    memory use the asynchronous abort mechanism, except for STREX, STREXB, STREXH, and

    STREXD.

    All store accesses to normal memory that is either inner cacheable or outer cacheable and

    any evictions from L1 or L2 cache do not cause an abort in the processor, instead they

    assert the nAXIERRIRQ pin. This is because the access that aborts might not relate

    directly back to a specific processor in the cluster.

    ...

    ...

    [注释] 以上内容只是针对Cortex-A7的。

Reply
  • Hi chinatiger,

    你可以参考Cortex-A7 TRM:

    7.4.1 External aborts handling

    ...

    ...

    All store accesses to Device, Strongly-ordered, or inner and outer Non-cacheable normal

    memory use the asynchronous abort mechanism, except for STREX, STREXB, STREXH, and

    STREXD.

    All store accesses to normal memory that is either inner cacheable or outer cacheable and

    any evictions from L1 or L2 cache do not cause an abort in the processor, instead they

    assert the nAXIERRIRQ pin. This is because the access that aborts might not relate

    directly back to a specific processor in the cluster.

    ...

    ...

    [注释] 以上内容只是针对Cortex-A7的。

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