DS-5 connect fail when cortex-r5 is in lock-step mode

Hi again ,

Thanks for the update and the confirmation of RPU_GLBL_CNTL value.

Using a Xilinx ZCU102 dev board and booting from SDCard with the A53_0 performing the boot, I am able to set up the R5's to be in lockstep mode with a DS-5 pre-connect script.

I can subsequently connect with DS-5 v5.29.2 and a DSTREAM unit (running 4.34.0 build 13 firmware as included with DS-5).

Please see the screenshot below :

Because the R5's are powered down prior to my connection, I used a script to set the R5's up to be in lockstep mode. As hopefully can be seen above, I can connect to R5_0 OK, and then if I also try connecting to R5_1 then as expected, it is not available and is being indicated as powered-down by DS-5.

So something is different about the way our targets are being initialised here I feel.

To investigate this further I will have to create an sdcard with the Cortex-R5 being the boot processor, but this might take me some little time as I do not have the required tools setup at the moment, it would be sometime next week before I could make much progress I'm afraid.

In the meantime, perhaps there is something different about the CPUs have been initialised with my script and the Xilinx tools ??

Also, could you just clarify which development board you are using please (weblink, part number...) ?

Regards,

Stuart

Hi again ,

Thanks for the update and the confirmation of RPU_GLBL_CNTL value.

Using a Xilinx ZCU102 dev board and booting from SDCard with the A53_0 performing the boot, I am able to set up the R5's to be in lockstep mode with a DS-5 pre-connect script.

I can subsequently connect with DS-5 v5.29.2 and a DSTREAM unit (running 4.34.0 build 13 firmware as included with DS-5).

Please see the screenshot below :

Because the R5's are powered down prior to my connection, I used a script to set the R5's up to be in lockstep mode. As hopefully can be seen above, I can connect to R5_0 OK, and then if I also try connecting to R5_1 then as expected, it is not available and is being indicated as powered-down by DS-5.

So something is different about the way our targets are being initialised here I feel.

To investigate this further I will have to create an sdcard with the Cortex-R5 being the boot processor, but this might take me some little time as I do not have the required tools setup at the moment, it would be sometime next week before I could make much progress I'm afraid.

In the meantime, perhaps there is something different about the CPUs have been initialised with my script and the Xilinx tools ??

Also, could you just clarify which development board you are using please (weblink, part number...) ?

Regards,

Stuart

Hi Stuart Hirons

Sorry for disturbing you. Is there any update for me?

Hi sorry, I am still sorting out a few tools issues to generate the appropriate SDCard image to boot the R5_0.

I'll let you know once I have any update

Hi, still battling with tools I am afraid, I need to install Vitis in order to generate a boot image for the Cortex-R5.

Sorry about this.

Thanks for your effort. Please let me know if any update.