DS-5 connect fail when cortex-r5 is in lock-step mode

Hi,

Thanks for your reply.Please see my reply below.

- what version of DS-5/Arm DS is in use

>>>

DS-5 Ultimate Edition
Version: 5.29.2
Build number: 5292005

- are you using the ZCU102 or Ultra96 board or 'something else' ?

>>>I am using CG serial.

- how are you booting the target board : from SDCard, flash, JTAG... ?

>>>boot from emmc.

- how are you configuring the R5's to be in lockstep mode, specifically what is the RPU_GLBL_CNTL set to, and when during the boot process ?

>>>set the destination cpu is "r5-lockstep" when generated boot.bin. The value of  RPU_GLBL_CNTL  is 0x50.

Hi,

Thanks for your reply.Please see my reply below.

- what version of DS-5/Arm DS is in use

>>>

DS-5 Ultimate Edition
Version: 5.29.2
Build number: 5292005

- are you using the ZCU102 or Ultra96 board or 'something else' ?

>>>I am using CG serial.

- how are you booting the target board : from SDCard, flash, JTAG... ?

>>>boot from emmc.

- how are you configuring the R5's to be in lockstep mode, specifically what is the RPU_GLBL_CNTL set to, and when during the boot process ?

>>>set the destination cpu is "r5-lockstep" when generated boot.bin. The value of  RPU_GLBL_CNTL  is 0x50.

Hi again ,

Thanks for the update and the confirmation of RPU_GLBL_CNTL value.

Using a Xilinx ZCU102 dev board and booting from SDCard with the A53_0 performing the boot, I am able to set up the R5's to be in lockstep mode with a DS-5 pre-connect script.

I can subsequently connect with DS-5 v5.29.2 and a DSTREAM unit (running 4.34.0 build 13 firmware as included with DS-5).

Please see the screenshot below :

Because the R5's are powered down prior to my connection, I used a script to set the R5's up to be in lockstep mode. As hopefully can be seen above, I can connect to R5_0 OK, and then if I also try connecting to R5_1 then as expected, it is not available and is being indicated as powered-down by DS-5.

So something is different about the way our targets are being initialised here I feel.

To investigate this further I will have to create an sdcard with the Cortex-R5 being the boot processor, but this might take me some little time as I do not have the required tools setup at the moment, it would be sometime next week before I could make much progress I'm afraid.

In the meantime, perhaps there is something different about the CPUs have been initialised with my script and the Xilinx tools ??

Also, could you just clarify which development board you are using please (weblink, part number...) ?

Regards,

Stuart

Hi,

Thanks for your support.

My development board is our own creation, and is based on Xilinx XCZU6CG-FFVB1156E SoC (https://www.digikey.com/product-detail/en/xilinx-inc/XCZU6CG-2FFVB1156E/XCZU6CG-2FFVB1156E-ND/6817801).

Hi Stuart Hirons

Sorry for disturbing you. Is there any update for me?

Hi sorry, I am still sorting out a few tools issues to generate the appropriate SDCard image to boot the R5_0.

I'll let you know once I have any update

Hi, still battling with tools I am afraid, I need to install Vitis in order to generate a boot image for the Cortex-R5.

Sorry about this.

Thanks for your effort. Please let me know if any update.

HI,

I am having difficulty setting the environment up for this, so can you please raise your issue at

https://developer.arm.com/support

and make it clear that is related to this post and I'll pick it up ASAP.

Sorry about this.

Regards,

Stuart

This is in fact by design and the Xilinx answer record on this issue is at

https://www.xilinx.com/support/answers/69183.html

This affects any debugger, not just Arm DS!

Regards,

Stuart