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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3640 Questions
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  • Not Answered

    cache invalid caused block 0

    • Cortex-A53
    • Arm Compiler 6
    • Cache coherency
    926 views
    0 replies
    Started over 2 years ago
    by WatterCutter
  • Not Answered

    Write-streaming support on Cortex-R5 0

    1244 views
    1 reply
    Latest over 2 years ago
    by yifanfeng
  • Not Answered

    Switching Exception level EL3 to EL1 0

    • Cortex-A53
    • AArch64
    • Baremetal
    1093 views
    0 replies
    Started over 2 years ago
    by Hariharan
  • Not Answered

    Possible to isolate cores into 2 groups with A720 + DSU-120 0

    804 views
    0 replies
    Started over 2 years ago
    by yifanfeng
  • Not Answered

    CPUACTLR_EL1 values labelled as debug purposes only 0

    844 views
    0 replies
    Started over 2 years ago
    by Josep J
  • Not Answered

    Effect of disabling branch predictor 0

    1332 views
    0 replies
    Started over 2 years ago
    by Josep J
  • Not Answered

    How assign partition scheme IDs to a core in one cluster? 0

    • Cortex-A55
    • Armv8-A
    • DynamIQ Shared Unit
    912 views
    0 replies
    Started over 2 years ago
    by Emmy0
  • Not Answered

    Event Register Semantics, Cortex M3 0

    721 views
    0 replies
    Started over 2 years ago
    by tobermory
  • Not Answered

    Debugging fails to load register view using aarch64-none-linux-gnu-gdb in linux platforms 0

    1254 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    mpidr doesn't work for all PE 0

    • Cortex-A65
    825 views
    0 replies
    Started over 2 years ago
    by ele
  • Answered

    Software level TrustZone for Cortex-M3/M4/M7 devices 0

    • AMBA 3 TrustZone Interrupt Controller (SP890)
    • Arm Trusted Firmware
    • Arm Architecture tools
    • TrustZone Controllers
    • Trusted Firmware-M
    • Armv7-M
    • TrustZone Address Space Controllers
    • GNU Arm
    • Trusted Execution Environment (TEE)
    • TrustZone
    3719 views
    4 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    how does processor identify itself 0

    1215 views
    1 reply
    Latest over 2 years ago
    by EllieC Arm Employee Badge
  • Not Answered

    Cortex R5 - TCM memory MPU setting 0

    1747 views
    1 reply
    Latest over 2 years ago
    by shalmana
  • Not Answered

    Cortex-A53 MMU: Contiguous bit at EL3 0

    • Cortex-A53
    • AArch64
    • Memory Management Unit (MMU)
    1020 views
    0 replies
    Started over 2 years ago
    by bradbqc
  • Not Answered

    AHB2 split and RETRY operations in Single Transfer type and last beat of Burst transfer type 0

    1478 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    TrustZone in ARM Cortex M3 0

    • Trusted Firmware-M
    • Cortex-M3
    • Trusted Execution Environment (TEE)
    2427 views
    5 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    how to do cache line scan test? 0

    • Cortex-A53
    • Cache Management
    • Cortex-A
    840 views
    0 replies
    Started over 2 years ago
    by WatterCutter
  • Not Answered

    "bus error" when using arm neon intrinsics "vld2q_f32 " on MT676x 0

    789 views
    0 replies
    Started over 2 years ago
    by jeffery-work
  • Not Answered

    pilatus pipeline depth 0

    1061 views
    0 replies
    Started over 2 years ago
    by minmin
  • Suggested Answer

    Crash on "push rbp" 0

    3035 views
    6 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
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