I'm reading L3 cache partitioning of Arm DynamIQ Shared Uint TRM for Cortex-A55.
The Doc describes that "L3 cache partitioning is achieved by partition scheme IDs and groups of cache ways" and "Each core in the cluster must be assigned to at least one of the eight partition scheme IDs.".
I don't understand the mapping between core and partition scheme IDs.
How assign partition scheme IDs to a core in one cluster?
Thanks for your attention!