cache invalid caused block

processor: cortex-a53 dual core

case: 

1. setup page table
2. r/w operations related with addr 0x80000000 (sram, mem attr: normal/wb/innershareable)
3. invalid data cache by using instrution 'DC IVAC'

cause:

1. data write to 0x80000000 acted on axi bus
2. following instrcution fetch stop (blocked by sth seems)

usage note:

 offer an assembly interface like:

.global invalid_addr

.type invalid_addr "function"

invalid_addr:

DC IVAC, X0

DSB SY

ISB

RET

called it:

invalid_addr(0x80000000)