Hi ARM expert,
When I am porting FreeRTOS to my Cortex M33 CPU, I met a secure hard fault exception because of running SVC instruction with BASEPRI_NS.BASEPRI[7:0] setting to 1.
I am curious why there is hard fault, because I think the value in BASEPRI is not equal or lower than the SVCall Priority Number which is configured in SHPR2.PRI_11. Let me explain my understanding here:
In my environment:
Configured interrupt priority == group priority,
If so, when BASEPRI_NS.BASEPRI[7:5] is set to 1, then the interrupts with priority <= 1 (on the contrary, with interrupt priority value >= 1) will be masked, and interrupts with priority value 0 (which has higher priority than BASEPRI) will not be masked.
But from my experimental phenomenon, it seems that when BASEPRI_NS.BASEPRI[7:5] is set to 1, the SVCall interrupt with priority value 0 is also treated as equal or lower priority than BASEPRI==1, which cause the hard fault.
Could you please help to explain it? And what is exact comparison formula in my case? Thank you very much!
Hi, your understand is correct. But as your setting is BASEPRI_NS, it only effects the non-secure interrupt. While there is a secure hard fault happening, it doesn't seem due to BASEPRI_NS. Could you please provide more information about that, like the code section about triggering exceptions and tarmac file? Thanks