Does Cortex-R5's L1 cache support write-streaming mode?
We find that memset 1M byte to ram on R5 with 32K dcache gets only 3 dcache miss, but this ram region is configured as cacheable, write-back, write allocate.
What could explain it?
It depends how we define "Cache Miss". Per R5 TRM (see above), it is a data read/write to normal Cacheable memory that caused a refill from the level 2 memory. So we you memset 1MB data, cache allocated but no need to refill them. I guess this this is the reason why you see such low cache miss rate.
Per my understanding, R5 does not support write streaming.