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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    GICv2 and GICv3 -- priority drop racing with deactivation through an LR 0

    • GICv2
    • GICv3/v4
    • Emulation & Virtualization
    1027 views
    0 replies
    Started over 2 years ago
    by Olivier Delande
  • Answered

    dma_map_resource() has a bad performance in pcie peer to peer transactions when iommu enabled in Linux 0

    • pcie
    • AArch64
    • SMMUv3
    • Armv8-A
    • Linux
    2082 views
    2 replies
    Latest over 2 years ago
    by Cailin Arm Employee Badge
  • Not Answered

    Unable to halt processor Arm cortex M3 more 0

    • Cortex-M3
    • Processors
    • SWD
    1072 views
    0 replies
    Started over 2 years ago
    by Mario_GT
  • Not Answered

    Pushing to the MSP stack instead when late arriving? 0

    • Armv7 Exception Model
    • R13 (SP Stack Pointer)
    • Armv7-M
    1028 views
    1 reply
    Latest over 2 years ago
    by ZacW
  • Answered

    AHB Bus Matrix Arbitration Delay 0

    • CMSDK
    1772 views
    2 replies
    Latest over 2 years ago
    by tjones95134
  • Not Answered

    Why branch to address with LSB=0 in non-secure state will trigger secure fault? 0

    • Control Flow Instructions
    • TrustZone
    1102 views
    0 replies
    Started over 2 years ago
    by Hiilda
  • Not Answered

    Problem with a Custom IP Slave AXI 0

    • FPGA Xilinx
    • AXI4
    2032 views
    3 replies
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    M23/TrustZone - failing to write SAU and SCB_NS 0

    • Cortex-M23
    • TrustZone
    2115 views
    5 replies
    Latest over 2 years ago
    by Hiilda
  • Not Answered

    Why function's address is loaded into VMA? 0

    • Cortex-M3
    • Memory
    931 views
    0 replies
    Started over 2 years ago
    by nmmn1359
  • Answered

    Armv9 RME Cache access and GPC sequence order 0

    3466 views
    8 replies
    Latest over 2 years ago
    by josecm
  • Not Answered

    Can you tie off TLB if you're not using virtual memory? 0

    1020 views
    1 reply
    Latest over 2 years ago
    by 42Bastian Schick
  • Suggested Answer

    Is microSCU required for multi-cores to maintain coherency? +1

    1491 views
    3 replies
    Latest over 2 years ago
    by tjones95134
  • Answered

    Cortex-A15: How to access the Revision ID register, REVIDR 0

    • Cortex-A15
    1243 views
    2 replies
    Latest over 2 years ago
    by TimF
  • Suggested Answer

    Difference in coding format. 0

    • Base ISAs
    • SIMD ISAs
    1169 views
    2 replies
    Latest over 2 years ago
    by BobP
  • Answered

    SVC instruction execution inside the hard fault handler 0

    2703 views
    4 replies
    Latest over 2 years ago
    by Sudhu145
  • Not Answered

    How to automatically detect Cortex M7 ALU overflow ?? 0

    • Interrupt Handling
    • Cortex-M7
    • Arm Compiler for Embedded FuSa
    1192 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    What is the unit of PMHF for R52 IP FMEDA 0

    • Cortex-R52
    716 views
    0 replies
    Started over 2 years ago
    by pengfu xie
  • Answered

    Equivalent of SSE4.2 needed for ARM support to CNDP Project 0

    2688 views
    6 replies
    Latest over 2 years ago
    by Annie
  • Not Answered

    ARMV8 arch64 how to handle bus error and interrupt occur together 0

    1888 views
    2 replies
    Latest over 2 years ago
    by Thomas Coding
  • Not Answered

    Cortex-M7 Failing to read PPB ROM table 0

    898 views
    0 replies
    Started over 2 years ago
    by Bert Hindle
<>
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