Hi ...
In the Cortex-R5 TRM, there are some restrictions for the AXI.
Such as, no transaction ever crosses a 32-byte boundary in memory for AXI transfer.
Is there any restriction for Cortex-R52 ?
Per our test of Cortex-R52, for the same code, if the code cross two cache line address range will spend much more time than within one cache line address range when I cache is disabled.
BR
Grace