Hello. I have a SOC containing a 4-core Cortex-A15 revision r2p4. REVIDR bits 1,3 and 9 are set. Very occasionally the processor is locking up.I've looked through the errata here... developer.arm.com/.../I think that the most likely candidate is 814169: "A series of store or PLDW instructions hitting the L2 cache in shared state in an ACE system might cause a deadlock".The erratum states "For the conditions to occur an A15 core or ACP needs to be doing write requests to a series of cache lines that have been accessed by another cacheable master in the system and are in the L2 cache in shared state."I have a few questions to clarify my understanding - basically I'm trying to work out which of the listed conditions can be generated solely from the A15 cores, and which of them require external actors connected to ACE.1) Is it possible for the L2 cache to enter the "shared state" by using only the A15 cores? Or does "shared state" require other peripherals?2) It states that "There is no workaround in an ACE system with multiple caching masters". Do the separate A15 cores count as multiple caching masters or does this require other peripheral(s)? 3) It states "If the six readUnique requests are unable to complete in the interconnect until a snoop request to the same tag bank completes, the A15 will deadlock." Under what circumstances would the readUnique request depend on a snoop? Could that happen with just the A15 cores, or is an external peripheral needed?4) Is it possible to have cache snooping enabled internally between the A15 cores, but disable the ACE system in software? Obviously I would then have to deal with coherency issues between peripherals which is very painful(!) - but would that be sufficient to stop this erratum occurring?Information on any of these would be really helpful. Many thanks!
I recommend raising an official support case from the support menu above.
Thanks Ronan. Support case created.