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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    Interruptible Instructions on Cortex-M4 0

    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    13054 views
    5 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM 0

    • L1
    • Cortex-A5
    • Cache
    • Cortex-A
    5485 views
    0 replies
    Started over 7 years ago
    by claudiu
  • Answered

    Bit-Banding. Only 1 bit at a time? 0

    • Cortex-M0
    • Cortex-M
    • C
    14478 views
    17 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Information about ARM System control registers. +1

    • Cortex-A53
    • Cortex-A
    8690 views
    7 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to access the system control register? +1

    • Cortex-A53
    • AArch64
    • Cortex-A
    • C
    • AArch32
    15241 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    which register are dedicated for each MPCore in ARMv8-A architecture? 0

    • AArch64
    • Armv8-A
    • Cortex-A
    9231 views
    4 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Port x86_64 Intrinsics to ARM64 equivalent +1

    • ifdef
    • else
    • x86
    • Arm Assembly Language (ASM)
    • Arm64
    • endif
    9781 views
    2 replies
    Latest over 7 years ago
    by aerodpe
  • Answered

    secure function call from none-secure side thread mode +1

    • TrustZone
    • Armv8-M
    • Memory
    8973 views
    1 reply
    Latest over 7 years ago
    by Miklos Balint Arm Employee Badge
  • Not Answered

    Calling None-Secure method directly from Secure world 0

    • TrustZone
    • Armv8-M
    • Block
    14411 views
    7 replies
    Latest over 7 years ago
    by Uma Ramalingam Arm Employee Badge
  • Answered

    GIC-400 controller virtual interrupt handling in VM and hypervisor +1

    • Cortex-A57
    • Generic Interrupt Controller
    • Cortex-A
    8269 views
    2 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    efficient c programming 0

    • Cortex-R
    • Cortex-M
    • C
    5672 views
    4 replies
    Latest over 7 years ago
    by Wenchuan2018
  • Answered

    Using arm softcore in Kintex 7 board 0

    • Keil MDK
    • Cortex-M
    3807 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Trustzone FIQ latency measurement When security extension is enabled +1

    • Armv7-A
    • Cortex-A
    • Cortex-A7
    • TrustZone
    6902 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Suggested Answer

    Where can i find resources about creating program on cortex-m7 from scratch? 0

    • Cortex-M7
    • Cortex-M
    2830 views
    1 reply
    Latest over 7 years ago
    by Sebastian Floss
  • Suggested Answer

    Which ARMv8 register controls cache partitioning 0

    • Cache
    • Armv8-A
    6917 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Is a DMB required between loading BASEPRI and storing BASEPRI_MAX? 0

    • Cortex-M7
    • Armv7-M
    • Cortex-M
    7888 views
    6 replies
    Latest over 7 years ago
    by Ramzyo
  • Not Answered

    Does Cortex R4x support SPI? 0

    • Cortex-R
    • Interface
    • Cortex-R4
    2279 views
    0 replies
    Started over 7 years ago
    by Anurag_Kumar
  • Answered

    Cortex-A7 Generic Timer Clock and Operation +1

    • Cortex-A
    • Cortex-A7
    10890 views
    4 replies
    Latest over 7 years ago
    by linda zhang
  • Answered

    What are the real benefits of implementing IDAU from the viewpoint of chip designers? 0

    • Address
    • ACE
    • AXI
    • Statement
    • TrustZone
    • Armv8-M
    • Secure Transactions
    • Memory
    8514 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    How to debug TF-M ns code on FVP_MPS2_AEMv8M? 0

    • Security
    • TrustZone
    • Armv8-M
    8905 views
    1 reply
    Latest over 7 years ago
    by Tao Lu
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Topics being discussed in this forum
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  • Arm Assembly Language (ASM)
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  • NEON
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