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L2 TLB internal memory access through RAMINDEX

Amitra29877

Hi Experts,

I need to access L2 TLB internal memory for A76 core (Section A6.6 of Cortex A76 TRM) . I was searching for an example code and found this for A57 core:

LDR X0, =0x0000000001000D80
SYS #0, c15, c4, #0, X0
DSB SY
ISB
MRS X1, S3_0_c15_c0_0 ; Move ILData0 register to X1
MRS X2, S3_0_c15_c0_1 ; Move ILData1 register to X2
MRS X3, S3_0_c15_c0_2 ; Move ILData2 register to X3
MRS X4, S3_0_c15_c0_3 ; Move ILData3 register to X4

My questions are:
1. which address is being accessed in the first LDR instruction? (0x0000000001000D80). What will be the equivalent address for A76 ?
2. I am novice and yet to start with the instruction manual. Can anyone explain on the 3rd and 4th instructions please? 
DSB SY
ISB

Regards,

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