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Hi all,
I am studying ARMv8_VSMA. I have a question about the XN bit in the table descriptor.
In the manual, there is an explanation about this as below.Execute-never controls determine whether instructions can be executed from a memory region.
Here is a stage 1 address translation(4K granule):TTBR_ELx--->L0 descriptor--->L1 descriptor--->L2 descriptor--->L3 descriptor--->4K page
If XN bit in the L0 table descriptor is set to 1, does that mean cpu can't fetch instructions from the address of L1 descriptor? ---If that is ture, whether XN is set or not should not affect the lookup of L1 because the address of L1 descriptor should store the L1 descriptor, not any instructions. Am I right?---If not, what is my misunderstanding?
Thank you.
If a L0 desc has XNTable bit set, the entire VA region (512GB when granule size is 4KB) under the control of that desc is considered non-executable, under the definition of that bit. The section "Hierarchical control of instruction fetching" has details.
If this is a question of whether one can point a PE to a table which stores the descriptors, and force it to run the descriptor-entry values as instructions, that would depend on how the table itself is mapped.
Thank you for the relay.
I think I have misunderstood its scope of action. when L0 desc has XNTable bit set, it affect all subsequent level(L1, L2, l3)，not only the L1 lookup. Is that right?
Yes.