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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3584 Questions
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  • Answered

    Where can I find the docments about how the ARM cortex-A series pipeline works? 0

    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    3311 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    infinite Break Points 0

    • Cortex-M3
    • Cortex-M
    6448 views
    8 replies
    Latest over 10 years ago
    by harshan
  • Not Answered

    Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore 0

    • Cortex-A9
    • Cortex-A
    4374 views
    2 replies
    Latest over 10 years ago
    by Niranjan Dighe
  • Answered

    In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many? 0

    • Cortex-A
    • Cortex-A7
    4332 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    clean and invalidate cache behavior before same address read +1

    • Cortex-A17
    • Cortex-A
    5711 views
    4 replies
    Latest over 10 years ago
    by loquat
  • Answered

    I2S with ARM M0 +1

    • Cortex-M0
    • Cortex-M
    8253 views
    3 replies
    Latest over 10 years ago
    by daith
  • Answered

    Where can I find the cortex-A7 related 8 stages pipeline docments? 0

    • Cortex-A
    • Cortex-A7
    4331 views
    2 replies
    Latest over 10 years ago
    by Kun.Niu
  • Answered

    If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region? 0

    • Cortex-A
    • Cortex-A7
    4753 views
    1 reply
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    In USB why VID(vendor id) , PID(Product id ) are required?? +1

    • Cortex-M
    24551 views
    5 replies
    Latest over 10 years ago
    by Mustafa S.
  • Answered

    Questions about Generic Timer in ARMv8 0

    • big.LITTLE
    • Armv7-A
    • Cortex-A9
    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    10380 views
    4 replies
    Latest over 10 years ago
    by wangchj
  • Answered

    Break Points and Watch Points +1

    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    5195 views
    1 reply
    Latest over 10 years ago
    by Mustafa S.
  • Answered

    question about arm cortex-a9 neon optimization(4x4 matrix mul) +1

    • Cortex-A9
    • NEON
    • Cortex-A
    5855 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Suggested Answer

    Address Space Identifier - ASID +1

    • Armv7-A
    • Armv7-R
    • Linux
    34756 views
    2 replies
    Latest over 10 years ago
    by Mike Clark
  • Answered

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave?? +1

    • AMBA
    • AXI
    • AXI4
    4357 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary? 0

    • AMBA
    • AXI
    9799 views
    5 replies
    Latest over 10 years ago
    by wangchj
  • Answered

    In NEON, have the three instructions( VCLS, VCLZ, VCNT), are they all count sign bit? 0

    • NEON
    • Cortex-A
    6019 views
    1 reply
    Latest over 10 years ago
    by Kun.Niu
  • Answered

    White Paper Document on Selection of Processors +1

    • Cortex-R
    • Cortex-A
    • Cortex-M
    6851 views
    4 replies
    Latest over 10 years ago
    by Efried
  • Answered

    What does this instruction do? 0

    • Armv7-A
    • Armv7-R
    • C
    7569 views
    7 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    Bus error while executing ARMv8 TLB instruction 0

    • Armv8-A
    9540 views
    5 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Please explain non-temporal example in programmer's guide +1

    • Cortex-A
    13659 views
    9 replies
    Latest over 10 years ago
    by daith
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