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I am running on cortex-A17.
when following,
step1: STR R0, [R1] ; [R1] is cacheable
step2: DCCIMVAC ; clean and invalidate cache
step3: LDR R0, [R1] ; memory read
Does step3 access L3(external memory) ?
Or access eviction-buffer in cortex-A17 ?
Or, unknown behavior?
If you had just performed a clean, then it would possible that the core would snoop the eviction buffer.
As you did a clean+invalidate the core has to re-read the location from the memory system.
(Assuming that the address passed to the data cache op is the same VA as in r0)
Additional,
step2': DMB (or DSB) <- It's require?
I am considering.
For step3 read memory, step2' is require.
Or not require?
If the STR, DCCIMVAC and LDR are all to the same (or overlapping) address - then the DMB is not required, as you have an address dependency.
OK.
I understood and It's too helpful.
Thanks for you.