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I am running on cortex-A17.
when following,
step1: STR R0, [R1] ; [R1] is cacheable
step2: DCCIMVAC ; clean and invalidate cache
step3: LDR R0, [R1] ; memory read
Does step3 access L3(external memory) ?
Or access eviction-buffer in cortex-A17 ?
Or, unknown behavior?
OK.
I understood and It's too helpful.
Thanks for you.