In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many bytes?
If you mean the software visible PC (i.e. what "MOV r0, pc" would return), then this is architectural and independent of the number of pipeline stages.
A2.3 ARM core registers ... PC, the program counter • When executing an ARM instruction, PC reads as the address of the current instruction plus 8. • When executing a Thumb instruction, PC reads as the address of the current instruction plus 4. • Writing an address to PC causes a branch to that address.
A2.3 ARM core registers
...
PC, the program counter
• When executing an ARM instruction, PC reads as the address of the current instruction plus 8.
• When executing a Thumb instruction, PC reads as the address of the current instruction plus 4.
• Writing an address to PC causes a branch to that address.
The reason for these offsets is historical, and maintained for backwards compatibility.