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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    Return address from FIQ_Handler. Do we come back to the next instruction? 0

    • Armv7-A
    • Armv7-R
    • Cortex-M
    4156 views
    3 replies
    Latest over 10 years ago
    by Harshdeep
  • Answered

    Cortex-A8 boot up cpsr status 0

    • Cortex-A
    • Cortex-A8
    • Linux
    5195 views
    3 replies
    Latest over 10 years ago
    by Harshdeep
  • Answered

    How to use the performance monitor of Cortex-A9? 0

    • Cortex-A9
    • Cortex-A
    6286 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Problems with  AXI4  write data channel 0

    • AMBA
    • AXI4
    6665 views
    6 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    Cortex-M7 "zero overhead loop" 0

    • Cortex-M7
    • Cortex-M
    • Cortex-M4
    10374 views
    6 replies
    Latest over 10 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    brk instrustion +1

    • Cortex-A53
    • AArch64
    • Cortex-A
    • C
    5732 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    ARM v8 secondary CPU bootup 0

    • AArch64
    • Armv8-A
    • TrustZone
    • C
    8886 views
    4 replies
    Latest over 10 years ago
    by Harish G
  • Answered

    shareability memory attribute 0

    • Cortex-A57
    • Cortex-A
    • Cortex-A8
    7113 views
    2 replies
    Latest over 10 years ago
    by hostia
  • Answered

    How to acknowledge/clear active interrupt in Cortex-M4 +1

    • Cortex-M
    • Cortex-M4
    15713 views
    4 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    ARMv8 EL1 MMU 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    10731 views
    6 replies
    Latest over 10 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    NEON SIMD Dn Register and Parallel Operations 0

    • 32-bit
    • NEON
    5775 views
    3 replies
    Latest over 10 years ago
    by Kenrick Aylesworth
  • Answered

    Does load/store-exclusive violate Hypervisor Transparency? 0

    • Armv7-A
    • Armv8-A
    4769 views
    1 reply
    Latest over 10 years ago
    by Matt Sealey Arm Employee Badge
  • Not Answered

    NEON-Advanced SIMD vs. SIMD 0

    • Armv6-A
    • NEON
    • Cortex-A
    15608 views
    5 replies
    Latest over 10 years ago
    by daith
  • Answered

    NEON SIMD Register Diagram 0

    • NEON
    • Cortex-A
    5688 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    The reason why the exception frame forms on PSP? 0

    • Cortex-A
    • Cortex-M
    11894 views
    15 replies
    Latest over 10 years ago
    by daith
  • Answered

    How to enable Neon in cortex A8? +1

    • NEON
    • Cortex-A
    • Cortex-A8
    13834 views
    9 replies
    Latest over 10 years ago
    by daith
  • Answered

    What is the effect of LDR r0, [r5, r6, LSL r2] 0

    • 32-bit
    8907 views
    2 replies
    Latest over 10 years ago
    by Phil Greco
  • Answered

    How many times same interrupt can be in pending state at a time? (In ARM CM-3) 0

    • Cortex-M3
    • Cortex-M
    4354 views
    2 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    why Interrupt 1023 (Spurious interrupt) happens when i set pagetable attribute on exynos5250? +1

    • Cortex-A15
    • Cache
    • Cortex-A
    • TrustZone
    7326 views
    6 replies
    Latest over 10 years ago
    by Yeo Reum Yun
  • Not Answered

    Continue the Target using Serial Wire Debug Protocol 0

    • Cortex-M3
    • Cortex-M
    5311 views
    8 replies
    Latest over 10 years ago
    by harshan
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