Can an ACE master have multiple write channels ?
e.g. AW_0, AW_1, W_0, W_1, B_0, B_1, AR, R, AC, CR, CD
Can this still be considered as an ACE-compliant component ?
Hello,
I think it would be implementation dependent.
By the way, why do you want the 2 channels?
Do you want to execute write interleave?
If it is not so, the multiple channel would be useless although I am not familiar to the ACE.
best regards,
Yasuhiko Koumoto.