Why does Cortex-R only support most two cores?

Hello,

the main reason fo two cores is to configure the lock-step system for the higher reliability.

One core is used for a master which will operate normally.

Another is used for a checker which compares its output with the master output on condition the common inputs.

Honestly speaking, the ideal configuration is to do a decision by majority by 3 cores.

However, the comparison logic would become more complex with 3 cores.

Actually, 2 core lock-step system is natural thing in the automotive area.

Best regards,

Yasuhiko Koumoto.

Hi laoniu_c,

Do you have a project in mind that would need more than 2 cores? In the Cortex-A space, multi-core systems typically have large, coherent memory systems. Coherency makes it easy to migrate tasks between cores, and share data between cores, but often at the cost of determinism and with additional system complexity. Most Cortex-R customers are interested in worst-case timing behaviour, so having a very deterministic system is important. The Cortex-R7 supports coherency up to a 2-core system, but further cores add complexity in areas such as the snoop-control unit that manages coherency between the cores. (While the Cortex-R5 supports a 2-core system and there is an external coherency port, the cores themselves are not coherent in hardware).

Fundamentally the architecture can support more than 2 cores, or you could build a system from multiple, 1-core processors (but you would have to manage any coherency requirements in software).

And of course as Yasuhiko Koumoto explained, many projects are using the second core as part of a dual-core lock step system, for additional safety - but this only gives the performance of a single core. However a majority decision with 3-cores adds additional challenges - for example if there is an error on the single input pin, this error will be seen by all 3 cores in the system. A true majority system may go as far as having different sensors for each part of the system etc - it's a very difficult problem to solve this within a single SoC.

If you can tell us a little more about the project you have in mind, it will be easier to answer any specific questions or concerns you have.

kind regards,

Jon