For the view of architecture, why the coprocessor is removed for A64 instruction set?
Hi,
Even in AArch32 the coprocessors are only conceptual, with the opcode space being used to access system registers (CP15), debug registers (CP14), and FP / NEON (CP10 & CP11). This is contrast to older versions of the architecture where there needed to be a way to access actual coprocessors in the system.
In AArch64, the conceptual coprocessors have been removed and we now only access system registers using MSR/MRS instructions with the target register's name.
Take for example CPACR_EL1, which is architecturally mapped to the AArch32 register CPACR. To access CPACR in AArch32 we need to use coprocessor instructions:
MRC p15,0,<Rt>,c1,c0,2 ; Read CPACR into Rt MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR
MRC p15,0,<Rt>,c1,c0,2 ; Read CPACR into Rt
MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR
Whereas to access CPACR_EL1 in AArch64 we just use the register name:
MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1
MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt
MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1
Hope that helps,
Ash.
I will say it ... Because it did more necessary ...
What Ash says...
Hardly anyone (including those of us in ARM) knows what MRC p15,0,<Rt>,c1,c0,2 does, without relying on comments in the code or checking the docs. The new System Register mnemonics just make life easier, because you can guess what they do. However "under the hood" they are still basically co-processor ops.