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Hi,
I find the following code snippet online on ARM state change. Although that whole material looks solid, the second line in the blue code below is puzzling.
add R1,PC,#1 ;Load address of SUB_BRANCH, Set for THUMB by adding 1
I don't see how the above line can get Load address of SUB_BRANCH address from PC. The whole article can be got from link:
https://www.cs.princeton.edu/courses/archive/fall12/cos375/ARMthumb.pdf
Is it an error, or I miss something on understanding it?
Thanks,
There are several ways to enter or leave the Thumb state properly. The usual method is via the Branch
and Exchange (BX) instruction. See also Branch, Link, and Exchange (BLX) if you're using an ARM with
version 5 architecture. During the branch, the CPU examines the least significant bit (LSb) of the
destination address to determine the new state. Since all ARM instructions will align themselves on either a
32- or 16-bit boundary, the LSB of the address is not used in the branch directly. However, if the LSB is 1
when branching from ARM state, the processor switches to Thumb state before it begins executing from
the new address; if 0 when branching from Thumb state, back to ARM state it goes.
Listing 1: How to change into Thumb state, then back
mov R0,#5 ;Argument to function is in R0
BX R1 ;R1 contains address of SUB_BRANCH+1
;Assembler-specific instruction to switch to Thumb
SUB_BRANCH:
BL thumb_sub ;Must be in a space of +/- 4 MB
add R1,#7 ;Point to SUB_RETURN with bit 0 clear
BX R1
;Assembler-specific instruction to switch to ARM
SUB_RETURN:
Listing 1 shows one example (not the only one) of using the BX instruction to go from ARM to Thumb state
and back. This example first switches to Thumb state, then calls a subroutine that was written in Thumb
code. Upon return from the subroutine, the system again switches back to ARM state; though this
assumes that R1 is preserved by the subroutine. The PC always contains the address of the instruction
that is being executed plus 8 (which happens to be SUB_BRANCH). The Thumb BL instruction actually
resolves into two instructions, so 8 bytes are used between SUB_BRANCH and SUB_RETURN.
Hello,
I'm sorry. I misunderstood your question.
In ARM mode, PC indicates 2 instructions ahead and PC of 'ADD R1,PC,#1' is the address of 'SUB_BRANCH'.
In the program sequence, the execution mode will switch from ARM to Thumb at the SUB_BRANCH and after SUB_BRANCH, the program will execute in Thumb mode.
And R1 is now 'SUB_BRANCH+1' and by adding to 7 it will become 'SUB_BRANCH+8'.
'SUB_BRANCH+8' is the address of 'SUB_RETURN' and the program jumps to the address of which LSB value is 0 and the execution mode will become from Thumb mode to ARM mode.
Best regards,
Yasuhiko Koumoto.