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What does it mean 'IT can be omitted'?

Hi,

When I read the following on ARM website, I don't understand the first line. When I change ITTE to TE (as 'IT can be omitted"), the assembler complains an error of this line.

Could you explain it to me?

Thanks,

  ITTE NE ; IT can be omitted

  ANDNE r0,r0,r1 ; 16-bit AND, not ANDS

  ADDSNE r2,r2,#1 ; 32-bit ADDS (16-bit ADDS does not set flags in IT block)

  MOVEQ r2,r3 ; 16-bit MOV

  ITT AL ; emit 2 non-flag setting 16-bit instructions

  ADDAL r0,r0,r1 ; 16-bit ADD, not ADDS

  SUBAL r2,r2,#1 ; 16-bit SUB, not SUB

  ADD r0,r0,r1 ; expands into 32-bit ADD

  IT NE

  ADD r0,r0,r1 ; syntax error: no condition code used in IT block

    ITT    EQ       

    MOVEQ  r0,r1

    BEQ    dloop

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  • Hello,

    let me a little correct my answer.

    The meaning of 'IT can be omitted' is that the armasm of the RealView tool-chains will generate automatically IT instruction on condition there are instructions which are added execution conditions.

    That is,

    the instruction sequence of

      ANDNE r0,r0,r1

      ADDSNE r2,r2,#1

      MOVEQ r2,r3

    will be interpreted as

      ITTE NE

      ANDNE r0,r0,r1

      ADDSNE r2,r2,#1

      MOVEQ r2,r3.

    However, GCC seems not to have such features.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • Hello,

    let me a little correct my answer.

    The meaning of 'IT can be omitted' is that the armasm of the RealView tool-chains will generate automatically IT instruction on condition there are instructions which are added execution conditions.

    That is,

    the instruction sequence of

      ANDNE r0,r0,r1

      ADDSNE r2,r2,#1

      MOVEQ r2,r3

    will be interpreted as

      ITTE NE

      ANDNE r0,r0,r1

      ADDSNE r2,r2,#1

      MOVEQ r2,r3.

    However, GCC seems not to have such features.

    Best regards,

    Yasuhiko Koumoto.

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