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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    ACE - ReadNoSnoop transaction +1

    • AMBA
    • ACE
    4549 views
    1 reply
    Latest over 9 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    how can i design APB to AHB bridge ?? 0

    • AXI
    • AHB
    11348 views
    1 reply
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Getting started on Cortex A5 interrupts 0

    • Cortex-A5
    • Generic Interrupt Controller
    • Cortex-A
    5841 views
    3 replies
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    I have an Arm 32-bit Cortex V3.10, Does anyone know the manufacturer/email? +1

    • 32-bit
    • Cortex-M3
    • Cortex-M
    9255 views
    4 replies
    Latest over 9 years ago
    by jeff
  • Answered

    PMU (Performance monitor Unit) 0

    • Raspberry Pi
    • Arm11
    • Performance Monitor Unit (PMU)
    8381 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Secure world entry request by normal world application 0

    • Armv7
    • Cortex-A9
    • Cortex-A
    • TrustZone
    8683 views
    6 replies
    Latest over 9 years ago
    by Rui
  • Answered

    How many peripherals can be connected to APB? 0

    • APB
    4270 views
    4 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    SC and SD states in case of ReadNoSnoop transactions +1

    • AMBA
    • ACE
    3925 views
    1 reply
    Latest over 9 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI? +1

    • Cortex-A53
    • AXI
    • Cortex-A
    • Linux
    12651 views
    2 replies
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    v7M debug architecture questions 0

    • Armv7-M
    • Cortex-M
    3939 views
    2 replies
    Latest over 9 years ago
    by cray
  • Not Answered

    Differences between Privilege Modes and Non-Privilege Mode ? 0

    • Cortex-A9
    • AArch64
    • Armv8-A
    • Cortex-A
    20952 views
    6 replies
    Latest over 9 years ago
    by Alex Lee
  • Answered

    How to deice debug target exception level of watchpoint on ARMv8 architecture 0

    • EL1
    • EL2
    • AArch64
    • Armv8
    6016 views
    2 replies
    Latest over 9 years ago
    by Myoungjae Kim
  • Answered

    arm v7AR debug architecture DCC register access 0

    • Armv7-A
    • Armv7-M
    6304 views
    3 replies
    Latest over 9 years ago
    by Michael Williams Arm Employee Badge
  • Answered

    Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9? +1

    • Cortex-A9
    • Cache
    • Cortex-A
    8410 views
    4 replies
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Exceptions levels in the ARMv8 architecture +1

    • Arm Trusted Firmware
    • Armv8
    8736 views
    1 reply
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Enabling NEON Instructions on Pixhawk 0

    • NEON
    • Cortex-M
    • Cortex-M4
    3967 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Not Answered

    coming from AVR 8-bitter,starting ARM CORTEX-M programming 0

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    • GNU
    8960 views
    5 replies
    Latest over 9 years ago
    by Tony Cook
  • Answered

    cmsis NVIC question. +1

    • Cortex-M0
    • Armv6-M
    • Cortex-M3
    • Cortex-M
    • CMSIS
    • C
    • Cortex-M4
    5026 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    Bootcode geneartion from C testcase for Cortex_R4 +1

    • Cortex-R4
    6689 views
    5 replies
    Latest over 9 years ago
    by raj
  • Answered

    MIPS Calculation on ARMv7 +1

    • Armv7-A
    • Armv7-M
    • Arm9
    12668 views
    5 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone