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Thank you for your understanding.
In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.
To translate this RTL to a revision information, it is stated that
"RTL release 0x9 denotes r3p3 code of the cache controller. See the Release Note for the
value of these bits for other releases."
Where can I find these release notes to understand the value read from this register ?
Best,
Vincent
Ok, I understand now. Thank you for the detailed answer !